US5726084A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for forming integrated circuit structure
Assignee: RPX Clearinghouse LLC
•
Filing: 1996-04-25
•
Granted: 1998-03-10
•
Expires: 2016-04-25
Abstract
Abstract A integrated circuit structure and a method of fabrication thereof are provided. In particular, fully planarized, trench isolated semiconductor regions, e.g. comprising doped polysilicon, are provided in an integrated circuit substrate. These polysilicon regions have a smooth surface, substantially coplanar with the substrate surface, provided by chemical mechanical polishing. The near zero topography substrate provides for formation thereon of integrated circuit structures including e.g. capacitors, resistors, thin film capacitors, and interconnects, in the polysilicon trench regions at the same process level as devices formed in the semiconductor substrate. Thus a simple and flexible process for formation of improved device structures is provided, compatible with known Bipolar, CMOS and Bipolar-CMOS processes.
Inventors
- 👤 John M. Boyd
- 👤 Joseph P. Ellul
- 👤 Sing P. Tay
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:12
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/40; H10P; H10P95/00; H10P95/06; H10P95/062; H10W10/01; H10W10/041
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
120 words
A method of fabrication of an integrated circuit structure comprising: providing an integrated circuit substrate having a planar surface and a plurality of steep-sided trenches defined therein; filling the trenches with at least one trench filling layer comprising a semiconductor material selected from the group consisting polycrystalline and amorphous semiconductor materials; planarizing the substrate surface by a step of chemical mechanical polishing to remove parts of the at least one trench filling layer extending above a surface of the substrate, thereby forming a plurality of trench regions filled with semiconductor material and each having a fully planarized surface substantially coplanar with the substrate surface; and then forming semiconductor devices in the semiconductor substrate and in the semiconductor filled trench regions.
Claim 2
Independent Claim
120 words
A method of fabrication of an integrated circuit structure comprising: providing an integrated circuit substrate having a planar surface and a plurality of steep-sided trenches defined therein; filling the trenches with at least one trench filling layer comprising a semiconductor material selected from the group consisting polycrystalline and amorphous semiconductor materials; planarizing the substrate surface by a step of chemical mechanical polishing to remove parts of the at least one trench filling layer extending above a surface of the substrate, thereby forming a plurality of trench regions filled with semiconductor material and each having a fully planarized surface substantially coplanar with the substrate surface; and then forming semiconductor devices in the semiconductor substrate and in the semiconductor filled trench regions.
Claim 3
Dependent Claim
45 words
A method according to claim 1 wherein the step of filling the trenches with at least one trench filling layer comprising a semiconductor material comprises lining the trench with a layer of dielectric material and then filling the trench with a layer of semiconductor material.
Claim 4
Dependent Claim
46 words
A method according to claim 1 wherein the step of filling the trenches with at least one trench filling layer comprising a semiconductor material comprises: depositing a conformal layer of dielectric in each trench and then filling each trench with a conformal layer of semiconductor material.
Claim 5
Independent Claim
166 words
A method of fabrication of an integrated circuit structure comprising: providing an integrated circuit substrate having a planar surface and a plurality of steep-sided trenches defined therein; filling the trenches by steps comprising: lining the trenches with a layer of dielectric and then filling the trenches with at least one trench filling layer comprising a semiconductor material; planarizing the substrate surface by a step of chemical mechanical polishing to remove parts of the at least one trench filling layer and layer of dielectric extending above a surface of the substrate, thereby forming a plurality of trench regions filled with semiconductor material and each having a fully planarized surface substantially coplanar with the substrate surface; and then forming semiconductor devices in the semiconductor substrate and in the semiconductor filled trench regions; wherein the step of filling the trenches with at least one trench filling layer comprising a semiconductor material comprises filling the trench with a semiconductor material selected from the group consisting polycrystalline silicon or amorphous silicon.
Claim 6
Independent Claim
166 words
A method of fabrication of an integrated circuit structure comprising: providing an integrated circuit substrate having a planar surface and a plurality of steep-sided trenches defined therein; filling the trenches by steps comprising: lining the trenches with a layer of dielectric and then filling the trenches with at least one trench filling layer comprising a semiconductor material; planarizing the substrate surface by a step of chemical mechanical polishing to remove parts of the at least one trench filling layer and layer of dielectric extending above a surface of the substrate, thereby forming a plurality of trench regions filled with semiconductor material and each having a fully planarized surface substantially coplanar with the substrate surface; and then forming semiconductor devices in the semiconductor substrate and in the semiconductor filled trench regions; wherein the step of filling the trenches with at least one trench filling layer comprising a semiconductor material comprises filling the trench with a semiconductor material selected from the group consisting polycrystalline silicon or amorphous silicon.
Claim 7
Independent Claim
142 words
A method of fabrication of an integrated circuit structure comprising: providing an integrated circuit substrate having a planar surface and a plurality of steep-sided trenches defined therein; filling the trenches by steps comprising: lining the trenches with a layer of dielectric and then filling the trenches with at least one trench filling layer comprising a semiconductor material; planarizing the substrate surface by a step of chemical mechanical polishing to remove parts of the at least one trench filling layer and layer of dielectric extending above a surface of the substrate, thereby forming a plurality of trench regions filled with semiconductor material and each having a fully planarized surface substantially coplanar with the substrate surface; and then forming semiconductor devices in the semiconductor substrate and in the semiconductor filled trench regions; wherein the substrate is provided having a chemical mechanical polish resistant layer.
Claim 8
Independent Claim
142 words
A method of fabrication of an integrated circuit structure comprising: providing an integrated circuit substrate having a planar surface and a plurality of steep-sided trenches defined therein; filling the trenches by steps comprising: lining the trenches with a layer of dielectric and then filling the trenches with at least one trench filling layer comprising a semiconductor material; planarizing the substrate surface by a step of chemical mechanical polishing to remove parts of the at least one trench filling layer and layer of dielectric extending above a surface of the substrate, thereby forming a plurality of trench regions filled with semiconductor material and each having a fully planarized surface substantially coplanar with the substrate surface; and then forming semiconductor devices in the semiconductor substrate and in the semiconductor filled trench regions; wherein the substrate is provided having a chemical mechanical polish resistant layer.
Claim 9
Independent Claim
152 words
A method of fabrication of an integrated circuit structure comprising: providing an integrated circuit substrate having a planar surface and a plurality of steep-sided trenches defined therein; filling the trenches by steps comprising: lining the trenches with a layer of dielectric and then filling the trenches with at least one trench filling layer comprising a semiconductor material; planarizing the substrate surface by a step of chemical mechanical polishing to remove parts of the at least one trench filling layer and layer of dielectric extending above a surface of the substrate, thereby forming a plurality of trench regions filled with semiconductor material and each having a fully planarized surface substantially coplanar with the substrate surface; and then forming semiconductor devices in the semiconductor substrate and in the semiconductor filled trench regions; wherein the step of lining the trenches with a layer of dielectric comprises depositing a conformal layer of dielectric in each trench.
Claim 10
Independent Claim
152 words
A method of fabrication of an integrated circuit structure comprising: providing an integrated circuit substrate having a planar surface and a plurality of steep-sided trenches defined therein; filling the trenches by steps comprising: lining the trenches with a layer of dielectric and then filling the trenches with at least one trench filling layer comprising a semiconductor material; planarizing the substrate surface by a step of chemical mechanical polishing to remove parts of the at least one trench filling layer and layer of dielectric extending above a surface of the substrate, thereby forming a plurality of trench regions filled with semiconductor material and each having a fully planarized surface substantially coplanar with the substrate surface; and then forming semiconductor devices in the semiconductor substrate and in the semiconductor filled trench regions; wherein the step of lining the trenches with a layer of dielectric comprises depositing a conformal layer of dielectric in each trench.
Claim 11
Dependent Claim
20 words
A method according to claim 4 wherein the polycrystalline silicon is deposited by chemical vapour deposition with in situ doping.
Claim 12
Dependent Claim
24 words
A method according to claim 4 wherein the polycrystalline silicon is deposited by chemical vapour deposition and subsequently doped by ion implantation and annealing.
Claim 13
Dependent Claim
42 words
A method according to claim 5 wherein providing the trench filling layers comprises providing another polish resistant layer, the polish resistant layer thereby forming a polish stop having a surface coplanar with that of the polish resistant layer of the substrate surface.
References Cited (Backward Citations)
US3484311A
Cited
US3578515A
Cited
US3579058A
Cited
JPS5723217A
Cited
JPS58168233A
Cited
JPS58220443A
Cited
JPS5914677A
Cited
JPS59232440A
Cited
JPS60154638A
Cited
JPS61281537A
Cited
US4886762A
Cited
JPS6240740A
Cited
JPS6293954A
Cited
JPS62125629A
Cited
JPS63292664A
Cited
JPS6420635A
Cited
JPS6444648A
Cited
US4758531A
Cited
US5298450A
Cited
US4839309A
Cited
JPH02151061A
Cited
US5302541A
Cited
JPH04144123A
Cited
US5477071A
Cited
US5407846A
Cited
US5508531A
Cited
US5275974A
Cited
US5394000A
Cited
US5316978A
Cited
US5352923A
Cited
US5362669A
Cited
US5411913A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-09 | 2001-09-08 | 2002-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-09 | 2005-09-08 | 2006-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-09 | 2009-09-08 | 2010-03-10 | $7700.00 | Window Closed / Lapsed |