US3579058A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor module and method of its production
Assignee: Arbeitsstelle fuer Molekularelektronik
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Filing: 1968-02-02
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Granted: 1971-05-18
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Expires: 1988-02-02
Abstract
Abstract A multilayer junction semiconductor device includes one semiconductive layer of a type of conductivity provided on its upper surface with a recess of a rectangular cross section. Vertical walls and corners of this recess are coated with a thin insulating layer, while the bottom thereof is open. Another semiconductive layer of an opposite type of conductivity is disposed within this recess, so that the critical PN junction area extends perpendicularly to the insulated vertical walls. The method of producing this device is based on the semiconductive layer inside said recess serving as an initial temporary substratum on which subsequent layers are precipitated.
Inventors
- 👤 Dietrich Armgarth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:10
CPC Classifications
H; H10; H10P; H10P95/00; H10D; H10D99/00; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/019; H10W10/10; Y; Y10; Y10S; Y10S148/00; Y10S148/085; Y10S148/122; Y10S148/145
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
48 words
The semiconductor device according to claim 1 further comprising a plurality of functional elements, the upper surfaces of said functional elements being leveled into a plane and provided with an additional nonconductive protective layer having apertures therein adapted to receive terminals and electrical connections of said functional elements.
Claim 2
Dependent Claim
31 words
The device according to claim 1, wherein said upper layer portion further comprises a diffused layer of a different type of conductivity than said upper layer to thereby create a transistor.
Claim 3
Independent Claim
286 words
A method of producing a semiconductor multilayer device having at least one functional semiconductor element with an increased breakdown voltage, comprising the steps of: providing a number of vertical recesses of a rectangular cross section in the upper surface of a semiconDuctive body of one conductivity type, coating the resulting recessed surface area with a uniformly thin nonconductive layer, removing a central portion of said nonconductive thin layer in the top surface region of said semiconductive body between two adjacent recesses to define an active area, whereby the periphery of said top surface region remains coated with said nonconductive layer, coating the resulting said surface area with a uniformly thick layer of a highly doped semiconductive material of said one type of conductivity, removing said highly doped material as deep as said nonconductive thin layer from a surface region of the resulting surface area which does not overlie said two adjacent recesses and said active area, coating the resulting upper surface area with a uniformly thick nonconductive layer, coating said thick nonconductive layer with a thick polycrystalline layer to form a substratum, and leveling the latter surface of said substratum into a plane, leveling the lower surface of said semiconductive body as deep as the embedded nonconductive thin layer, redoping the portion of said semiconductive body exposed by said last-mentioned leveling step to have the opposite type of conductivity to a determined depth, whereby a PN junction is formed in said remaining semiconductive body which extends perpendicularly to the vertical portions of said thin nonconductive layer, and producing an additional nonconductive protection layer on the exposed surface of said semiconductive body, and forming an aperture in said additional nonconductive protection layer for making electrical connections therein.
Claim 4
Independent Claim
252 words
A method of producing a semiconductor multilayer device having at least one functional semiconductor element with an increased breakdown voltage, comprising the steps of providing a number of vertical recesses of a rectangular cross section in the upper surface of a semiconductive body of one conductivity type, coating the resulting recessed surface area with a uniformly thin nonconductive layer, removing a central portion of said thin nonconductive layer overlying the upper surface of said semiconductive body between two adjacent recesses to define an active area of the functional element, coating the resulting surface area overlying said two adjacent recesses and active area with a uniformly thick layer of a highly doped semiconductive material of said one type of conductivity to define an area where a functional element is to be located, coating the resulting upper surface area with a uniformly thick nonconductive layer coating said thick nonconductive layer with a thick polycrystalline layer and leveling the latter into a plane, leveling the lower surface of said semiconductor body as deep as the embedded nonconductive thin layer, redoping the portion of the semiconductive body exposed by said last-mentioned leveling step to have the opposite type of conductivity to a determined depth, whereby a p-n junction is formed in the remaining semiconductive body which extends perpendicularly to the vertical portions of said thin nonconductive layer, and producing an additional nonconductive thin layer on the exposed surface of said semiconductive body, and forming an aperture in said additional nonconductive protection layer for receiving electrical connections.
Claim 5
Independent Claim
262 words
A method of producing a semiconductor multilayer device having at least one functional semiconductor element with an increased breakdown voltage, comprising the steps of providing a number of vertical recesses of a rectangular cross section in the upper surface of a semiconductive body, coating the resulting surface area with a uniformly thick nonconductive layer, removing said thick nonconductive layer from the profiled surface region overlying two consecutive recesses and the surface area between said recesses to define an area of a functional element, coating the open profiled surface region wIth a thin nonconductive layer and removing the latter only in the central region of said surface area between said recesses, coating the resulting upper surface area with a uniformly thick layer of a highly doped semiconductive material of one type of conductivity, levelling said thick nonconductive layer and said highly doped semiconductive layer in one plane, coating the resulting plane with a uniformly thin nonconducting intermediate layer, coating the intermediate layer with a thick semiconductive layer and levelling the latter into a plane, levelling the lower surface of the semiconductive body as deep as to the embedded thin nonconductive layer, redoping the portion of the semiconductive body exposed by said last-mentioned levelling step to have the opposite type of conductivity to a determined depth, whereby a PN junction is formed in said remaining semiconductive body which extends perpendicularly to the vertical portions of said thin nonconductive layer, producing an additional nonconductive protection layer on the upper surface of the latter, and forming an aperture in said protection layer for receiving electrical connections.
Claim 6
Independent Claim
205 words
A method of producing a semiconductive device comprising the steps of providing a silicon semiconductive body with a number of vertical recesses of rectangular cross section to serve as a temporary substratum, insulating the profiled area between two adjacent recesses by means of a thin nonconductive layer of a silicon compound, removing said thin nonconductive layer from a portion of the region intermediate the recesses, precipitating a thick highly doped semiconductive material onto said profiled area, insulating the upper surface of the precipitated material by means of a thick nonconductive layer and depositing a thick polycrystalline semiconductive layer thereupon, levelling said polycrystalline layer to a plane to serve as a final substratum of the device, levelling said temporary substratum as deep as to the thin nonconductive layer, redoping said temporary substratum exposed by said last-mentioned levelling step, by a diffusion process, to have the opposite conductivity to a determined depth, whereby a PN junction is formed in said temporary substratum extending perpendicularly to the vertical portions of said thin nonconductive layer, and whereby a nonconductive protection layer is simultaneously formed on the surface of said redoped temporary substratum, and forming an aperture in said protection layer for making electrical connections to said redoped temporary substratum.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-17 | 1974-11-16 | 1975-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-17 | 1978-11-16 | 1979-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-17 | 1982-11-16 | 1983-05-18 | $7700.00 | Window Closed / Lapsed |