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US5411913A Expired / Lapsed US ⏱️ 0.0 years remaining

Simple planarized trench isolation and field oxide formation using poly-silicon

Assignee: National Semiconductor Corp
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Filing: 1994-04-29
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Granted: 1995-05-02
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Expires: 2014-04-29
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Abstract

Abstract A device isolation scheme that is particularly suited to the fabrication of high density, high performance CMOS, bipolar, or BiCMOS devices, and overcomes many of the problems associated with existing isolation methods. Photolithographic techniques are used to define active regions on a substrate. Using the photoresist as a mask for the active regions, the silicon in the inactive regions is etched. A pad oxide layer and nitride layer are then formed on the substrate. A layer of oxide is then deposited and photolithographic techniques are again used to define the locations for desired trench structures. After removal of the remaining photoresist, deep trenches are etched in the silicon substrate. An oxidation step is then carried out to provide a layer of oxide lining the trenches, followed by deposition of a layer of poly-silicon over the substrate, filling the trenches. The poly-silicon layer is etched back, removing it from the tops of the trenches and the field regions, and leaving a poly-silicon spacer on the sides of those portions of the previously deposited oxide layer which cover the active regions. The spacers are used to align a photoresist mask which is used to etch away the oxide layer on top of the active regions. The spacers are then removed while keeping the photoresist mask intact, thereby protecting the poly-silicon on top of the trenches. The photoresist mask is then removed and the poly-silicon on top of each trench is oxidized to cap the trench. The result is a highly planar surface in which active regions are separated by field oxide or poly-silicon filled trenches.

Inventors

  • 👤 Rashid Bashir
  • 👤 Francois Hebert
  • 👤 Datong Chen

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 15:12
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/06; H10P95/062; H10P95/064; H10P95/066; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/40

Claims Analysis

Total Claims: 23
Claim 1
Independent Claim 228 words
A method for electrically isolating individual active device regions of an integrated circuit fabricated in a semiconductor substrate, the method comprising: defining active and inactive regions on the substrate; etching the substrate in the inactive regions to form an etched portion of the substrate; depositing a layer of pad oxide on the resulting substrate; depositing a layer of nitride on the pad oxide layer; depositing a first oxide layer over the substrate, wherein the first oxide layer covers the previously deposited pad oxide and nitride layers and forms a step as a result of the etching step; patterning the first oxide layer to serve as a mask to define one or more deep trenches in the inactive regions of the substrate; etching one or more of the previously defined deep trenches into the silicon substrate; forming a second oxide layer on a wall or walls of the deep trenches; depositing a layer of poly-silicon over the substrate, wherein the poly-silicon fills the deep trenches and covers the first oxide layer; etching the poly-silicon layer to remove the poly-silicon from the inactive regions and to form a poly-silicon spacer on the sides of the step; and aligning a mask over the etched portions of the substrate and having an edge over the poly-silicon spacer such that a portion of the first oxide layer overlying the active regions is exposed.
Claim 2
Independent Claim 228 words
A method for electrically isolating individual active device regions of an integrated circuit fabricated in a semiconductor substrate, the method comprising: defining active and inactive regions on the substrate; etching the substrate in the inactive regions to form an etched portion of the substrate; depositing a layer of pad oxide on the resulting substrate; depositing a layer of nitride on the pad oxide layer; depositing a first oxide layer over the substrate, wherein the first oxide layer covers the previously deposited pad oxide and nitride layers and forms a step as a result of the etching step; patterning the first oxide layer to serve as a mask to define one or more deep trenches in the inactive regions of the substrate; etching one or more of the previously defined deep trenches into the silicon substrate; forming a second oxide layer on a wall or walls of the deep trenches; depositing a layer of poly-silicon over the substrate, wherein the poly-silicon fills the deep trenches and covers the first oxide layer; etching the poly-silicon layer to remove the poly-silicon from the inactive regions and to form a poly-silicon spacer on the sides of the step; and aligning a mask over the etched portions of the substrate and having an edge over the poly-silicon spacer such that a portion of the first oxide layer overlying the active regions is exposed.
Claim 3
Dependent Claim 46 words
The method of claim 1, further comprising: removing the first oxide layer from the active regions; removing the poly-silicon spacer; removing the remaining portions of the mask previously aligned over the etched portions of the substrate; and oxidizing the poly-silicon on top of the deep trenches.
Claim 4
Dependent Claim 29 words
The method of claim 1, wherein the poly-silicon spacer is laterally displaced from the active regions by a distance approximately equal to the thickness of the first oxide layer.
Claim 5
Dependent Claim 39 words
The method of claim 2, wherein the spacers act as a self-aligned mask permitting a portion of the oxide layer lying next to the spacers to be etched to form a planar field oxide relative to the active regions.
Claim 6
Dependent Claim 16 words
The method of claim 1, wherein the first oxide layer is low temperature deposited oxide (LTO).
Claim 7
Dependent Claim 14 words
The method of claim 1, wherein the first oxide layer is tetra-ethyl-ortho-silicate (TEOS) oxide.
Claim 8
Dependent Claim 18 words
The method of claim 1, wherein the deep trench is etched by a reactive ion etching (RIE) process.
Claim 9
Dependent Claim 20 words
The method of claim 1, wherein the deep trench is etched by a magnetically enhanced reactive ion etching (RIE) process.
Claim 10
Dependent Claim 17 words
The method of claim 1, wherein the deep trench is etched by an electron-cyclotron resonance etch process.
Claim 11
Dependent Claim 17 words
The method of claim 1, wherein the poly-silicon is etched by a reactive ion etching (RIE) process.
Claim 12
Dependent Claim 19 words
The method of claim 1, wherein the poly-silicon is etched by a magnetically enhanced reactive ion etching (RIE) process.
Claim 13
Dependent Claim 16 words
The method of claim 1, wherein the poly-silicon is etched by an electron-cyclotron resonance etch process.
Claim 14
Independent Claim 171 words
A method for electrically isolating individual active device regions of an integrated circuit fabricated in a semiconductor substrate, the method comprising: defining active and inactive regions on the substrate; etching the substrate in the inactive regions to form an etched portion of the substrate; depositing a layer of pad oxide on the resulting substrate; depositing a layer of nitride on the pad oxide layer; depositing a first oxide layer over the substrate, wherein the first oxide layer covers the previously deposited pad oxide and nitride layers and forms a step as a result of the etching step; depositing a layer of poly-silicon over the substrate, wherein the poly-silicon covers the first oxide layer; etching the poly-silicon layer to remove the poly-silicon from the inactive regions and to form a poly-silicon spacer on the sides of the step; and aligning a mask over the etched portions of the substrate and having an edge over the poly-silicon spacer such that a portion of the first oxide layer overlying the active regions is exposed.
Claim 15
Independent Claim 171 words
A method for electrically isolating individual active device regions of an integrated circuit fabricated in a semiconductor substrate, the method comprising: defining active and inactive regions on the substrate; etching the substrate in the inactive regions to form an etched portion of the substrate; depositing a layer of pad oxide on the resulting substrate; depositing a layer of nitride on the pad oxide layer; depositing a first oxide layer over the substrate, wherein the first oxide layer covers the previously deposited pad oxide and nitride layers and forms a step as a result of the etching step; depositing a layer of poly-silicon over the substrate, wherein the poly-silicon covers the first oxide layer; etching the poly-silicon layer to remove the poly-silicon from the inactive regions and to form a poly-silicon spacer on the sides of the step; and aligning a mask over the etched portions of the substrate and having an edge over the poly-silicon spacer such that a portion of the first oxide layer overlying the active regions is exposed.
Claim 16
Dependent Claim 37 words
The method of claim 13, further comprising: removing the first oxide layer from the active regions; removing the poly-silicon spacer; and removing the remaining portions of the mask previously aligned over the etched portions of the substrate.
Claim 17
Dependent Claim 29 words
The method of claim 13, wherein the poly-silicon spacer is laterally displaced from the active regions by a distance approximately equal to the thickness of the first oxide layer.
Claim 18
Dependent Claim 40 words
The method of claim 14, wherein the spacers act as a self-aligned mask permitting a portion of the first oxide layer lying next to the spacers to be etched to form a planar field oxide relative to the active regions.
Claim 19
Dependent Claim 16 words
The method of claim 13, wherein the first oxide layer is low temperature deposited oxide (LTO).
Claim 20
Dependent Claim 14 words
The method of claim 13, wherein the first oxide layer is tetra-ethyl-ortho-silicate (TEOS) oxide.
Claim 21
Dependent Claim 17 words
The method of claim 13, wherein the poly-silicon is etched by a reactive ion etching (RIE) process.
Claim 22
Dependent Claim 19 words
The method of claim 13, wherein the poly-silicon is etched by a magnetically enhanced reactive ion etching (RIE) process.
Claim 23
Dependent Claim 16 words
The method of claim 13, wherein the poly-silicon is etched by an electron-cyclotron resonance etch process.

References Cited (Backward Citations)

USRE34400E Cited
JPS6167932A Cited
US4879254A Cited
JPH01217964A Cited
US5294296A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-05-01 1998-10-31 1999-05-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-05-01 2002-10-31 2003-05-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-05-01 2006-10-31 2007-05-02 $7700.00 Window Closed / Lapsed

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