US5706296A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bi-directional scan design with memory and latching circuitry
Assignee: Texas Instruments Inc
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Filing: 1995-02-28
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Granted: 1998-01-06
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Expires: 2015-02-28
Abstract
Abstract A scan cell (51) for use at an input/output terminal includes memory circuitry (Mem 1) for storing test data from a test data path, and a latching circuit (S4, LOB; S6, LIB) connected to the memory circuitry for receiving and selectively latching the test data stored in the memory circuitry. The input/output terminal has an input buffer (IB) and an output buffer (3SOB) associated therewith, and the latching circuit includes one of the input buffer and the output buffer.
Inventors
- 👤 Lee D. Whetsel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:13
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
143 words
An electrical circuit, comprising: functional circuitry for performing normal operating functions of the electrical circuit; a terminal which is accessible externally of said electrical circuit; an input buffer coupled to said functional circuitry and said externally accessible terminal for driving into said functional circuitry input signals received at said externally accessible terminal; an output buffer coupled to said functional circuitry and said externally accessible terminal for receiving output signals from said functional circuitry and driving said output signals to said externally accessible terminal; a test data path for providing test data; memory circuitry coupled to said test data path for storing test data received from said test data path; and a latching circuit connected to said memory circuitry for receiving and selectively latching test data stored in said memory circuitry, said latching circuit including one of said input buffer and said output buffer.
Claim 2
Dependent Claim
143 words
An electrical circuit, comprising: functional circuitry for performing normal operating functions of the electrical circuit; a terminal which is accessible externally of said electrical circuit; an input buffer coupled to said functional circuitry and said externally accessible terminal for driving into said functional circuitry input signals received at said externally accessible terminal; an output buffer coupled to said functional circuitry and said externally accessible terminal for receiving output signals from said functional circuitry and driving said output signals to said externally accessible terminal; a test data path for providing test data; memory circuitry coupled to said test data path for storing test data received from said test data path; and a latching circuit connected to said memory circuitry for receiving and selectively latching test data stored in said memory circuitry, said latching circuit including one of said input buffer and said output buffer.
Claim 3
Dependent Claim
141 words
An electrical circuit, comprising: functional circuitry for performing normal operating functions of the electrical circuit; a terminal which is accessible externally of said electrical circuit; an input buffer coupled to said functional circuitry and said externally accessible terminal for driving into said functional circuitry input signals received at said externally accessible terminal; an output buffer coupled to said functional circuitry and said externally accessible terminal for receiving output signals from said functional circuitry and driving said output signals to said externally accessible terminal; a test data path for providing test data; memory circuitry coupled to said test data path for storing test data received from said test data path; and a latching circuit connected to said memory circuitry for receiving and selectively latching test data stored in said memory circuitry, said latching circuit including said input buffer and said output buffer.
Claim 4
Dependent Claim
141 words
An electrical circuit, comprising: functional circuitry for performing normal operating functions of the electrical circuit; a terminal which is accessible externally of said electrical circuit; an input buffer coupled to said functional circuitry and said externally accessible terminal for driving into said functional circuitry input signals received at said externally accessible terminal; an output buffer coupled to said functional circuitry and said externally accessible terminal for receiving output signals from said functional circuitry and driving said output signals to said externally accessible terminal; a test data path for providing test data; memory circuitry coupled to said test data path for storing test data received from said test data path; and a latching circuit connected to said memory circuitry for receiving and selectively latching test data stored in said memory circuitry, said latching circuit including said input buffer and said output buffer.
Claim 5
Dependent Claim
151 words
An electrical circuit, comprising: functional circuitry for performing normal operating functions of the electrical circuit; a terminal which is accessible externally of said electrical circuit; an input buffer coupled to said functional circuitry and said externally accessible terminal for driving into said functional circuitry input signals received at said externally accessible terminal; an output buffer coupled to said functional circuitry and said externally accessible terminal for receiving output signals from said functional circuitry and driving said output signals to said externally accessible terminal; a test data path for providing test data; memory circuitry coupled to said test data path for storing test data received from said test data path; and a latching circuit connected to said memory circuitry for receiving and selectively latching test data stored in said memory circuitry, said latching circuit including said output buffer, and said latching circuit operable to resolve voltage contention at said externally accessible terminal.
Claim 6
Dependent Claim
151 words
An electrical circuit, comprising: functional circuitry for performing normal operating functions of the electrical circuit; a terminal which is accessible externally of said electrical circuit; an input buffer coupled to said functional circuitry and said externally accessible terminal for driving into said functional circuitry input signals received at said externally accessible terminal; an output buffer coupled to said functional circuitry and said externally accessible terminal for receiving output signals from said functional circuitry and driving said output signals to said externally accessible terminal; a test data path for providing test data; memory circuitry coupled to said test data path for storing test data received from said test data path; and a latching circuit connected to said memory circuitry for receiving and selectively latching test data stored in said memory circuitry, said latching circuit including said output buffer, and said latching circuit operable to resolve voltage contention at said externally accessible terminal.
Claim 7
Dependent Claim
192 words
An electrical circuit, comprising: Functional circuitry for performing normal operating functions of the electrical circuit; a terminal which is accessible externally of said electrical circuit; an input buffer coupled to said functional circuitry and said externally accessible terminal for driving into said functional circuitry input signals received at said externally accessible terminal; an output buffer coupled to said functional circuitry and said externally accessible terminal for receiving output signals from said functional circuitry and driving said output signals to said externally accessible terminal; a test data path for providing test data; first memory circuitry coupled to said test data path for storing test data received from said test data path; a first latching circuit connected to said first memory circuitry for receiving and selectively latching test data stored in said first memory circuitry, said first latching circuit including said input buffer; second memory circuitry coupled to said test data path for storing test data received from said test data path; and a second latching circuit connected to said second memory circuitry for receiving and selectively latching test data stored in said second memory circuitry, said second latching circuit including said output buffer.
Claim 8
Dependent Claim
192 words
An electrical circuit, comprising: Functional circuitry for performing normal operating functions of the electrical circuit; a terminal which is accessible externally of said electrical circuit; an input buffer coupled to said functional circuitry and said externally accessible terminal for driving into said functional circuitry input signals received at said externally accessible terminal; an output buffer coupled to said functional circuitry and said externally accessible terminal for receiving output signals from said functional circuitry and driving said output signals to said externally accessible terminal; a test data path for providing test data; first memory circuitry coupled to said test data path for storing test data received from said test data path; a first latching circuit connected to said first memory circuitry for receiving and selectively latching test data stored in said first memory circuitry, said first latching circuit including said input buffer; second memory circuitry coupled to said test data path for storing test data received from said test data path; and a second latching circuit connected to said second memory circuitry for receiving and selectively latching test data stored in said second memory circuitry, said second latching circuit including said output buffer.
Claim 9
Dependent Claim
143 words
An electrical circuit, comprising: functional circuitry for performing normal operating functions of the electrical circuit; a terminal which is accessible externally of said electrical circuit; an output buffer coupled to said functional circuitry and said externally accessible terminal for receiving output signals from said functional circuitry and driving said output signals to said externally accessible terminal; an input buffer having an input and an output, said input coupled to said externally accessible terminal for driving to said output signals received at said externally accessible terminal; a test data path for providing test data; memory circuitry coupled to said test data path for storing test data received from said test data path; and a latching circuit connected to said memory circuitry for receiving and selectively latching test data stored in said memory circuitry, said latching circuit including said input buffer and said output buffer.
Claim 10
Dependent Claim
143 words
An electrical circuit, comprising: functional circuitry for performing normal operating functions of the electrical circuit; a terminal which is accessible externally of said electrical circuit; an output buffer coupled to said functional circuitry and said externally accessible terminal for receiving output signals from said functional circuitry and driving said output signals to said externally accessible terminal; an input buffer having an input and an output, said input coupled to said externally accessible terminal for driving to said output signals received at said externally accessible terminal; a test data path for providing test data; memory circuitry coupled to said test data path for storing test data received from said test data path; and a latching circuit connected to said memory circuitry for receiving and selectively latching test data stored in said memory circuitry, said latching circuit including said input buffer and said output buffer.
Claim 11
Dependent Claim
28 words
The circuit of claim 5, wherein said latching circuit includes a feedback element connected between said output of said input buffer and an input of said output buffer.
Claim 12
Dependent Claim
13 words
The circuit of claim 6, wherein said feedback element is a transmission gate.
Claim 13
Dependent Claim
13 words
The circuit of claim 6, wherein said feedback element is a 2-state buffer.
Claim 14
Dependent Claim
13 words
The circuit of claim 6, wherein said feedback element is a 3-state buffer.
Claim 15
Dependent Claim
24 words
The circuit of claim 6, wherein said latching circuit includes a switch connected between said functional circuitry and said input of said output buffer.
Claim 16
Dependent Claim
12 words
The circuit of claim 10, wherein said switch is a transmission gate.
Claim 17
Dependent Claim
12 words
The circuit of claim 10, wherein said switch is a 3-state buffer.
Claim 18
Dependent Claim
28 words
The circuit of claim 2, wherein said latching circuit includes a feedback element connected between an output of said input buffer and an input of said output buffer.
Claim 19
Dependent Claim
13 words
The circuit of claim 13, wherein said feedback element is a transmission gate.
Claim 20
Dependent Claim
13 words
The circuit of claim 13, wherein said feedback element is a 2-state buffer.
Claim 21
Dependent Claim
13 words
The circuit of claim 13, wherein said feedback element is a 3-state buffer.
Claim 22
Dependent Claim
24 words
The circuit of claim 13, wherein said latching circuit includes a switch connected between said functional circuitry and said input of said output buffer.
Claim 23
Dependent Claim
12 words
The circuit of claim 17, wherein said switch is a transmission gate.
Claim 24
Dependent Claim
12 words
The circuit of claim 17, wherein said switch is a 3-state buffer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-01-05 | 2001-07-07 | 2002-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-01-05 | 2005-07-07 | 2006-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-01-05 | 2009-07-07 | 2010-01-06 | $7700.00 | Window Closed / Lapsed |