US5373514A
Expired / Lapsed
US
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Three-state bus structure and method for generating test vectors while avoiding contention and/or floating outputs on the three-state bus
Assignee: Synopsys Inc
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Filing: 1993-01-08
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Granted: 1994-12-13
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Expires: 2013-01-08
Abstract
Abstract A structure and method, useful in a test pattern generation system, for evaluating control and data input signals to a three state bus to determine whether the control input signals result in either a contention on the three state bus or floating of the three state bus is disclosed. Two parallel logic networks are used. A first logic network receives both the control input signals and data input signals and in turn generates an output signal that is the output signal of the three state bus. The second logic network receives only the control input signals and in turn generates an output signal having a first predetermined value when the bus output signal is valid and a second predetermined value when either a contention exists on the three state bus or the three state bus is floating. Selection of test vectors that produce only control signals that in turn produce an output signal from the second logic network having the first predetermined value results in selection of only valid test vectors.
Inventors
- 👤 Hi K. Ma
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:36
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318342; G01R31/318357; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
183 words
A structure for identifying digital circuit data input and control input signals to a three state bus that result in either contentions or floating of said three state bus, said structure comprising: means, responsive to said three state bus data input and control input signals, for simulating digital logic signal propagation through said three state bus wherein the output signal of said simulating means is the response of said three state bus to said three state bus data input and control input signals; and means, responsive to said control input signals, for (i) detecting contentions on said three state bus and (ii) detecting floating of said three state bus; wherein the output signal of said detecting means has (i) a first constant predetermined logic value in the absence of a contention on and floating of said three state bus and (ii) a second constant predetermined logic value in the presence of each condition in the group of conditions consisting of contentions on and floating of said three state bus thereby identifying the digital circuit control input signals that result in contentions and floating.
Claim 2
Dependent Claim
183 words
A structure for identifying digital circuit data input and control input signals to a three state bus that result in either contentions or floating of said three state bus, said structure comprising: means, responsive to said three state bus data input and control input signals, for simulating digital logic signal propagation through said three state bus wherein the output signal of said simulating means is the response of said three state bus to said three state bus data input and control input signals; and means, responsive to said control input signals, for (i) detecting contentions on said three state bus and (ii) detecting floating of said three state bus; wherein the output signal of said detecting means has (i) a first constant predetermined logic value in the absence of a contention on and floating of said three state bus and (ii) a second constant predetermined logic value in the presence of each condition in the group of conditions consisting of contentions on and floating of said three state bus thereby identifying the digital circuit control input signals that result in contentions and floating.
Claim 3
Dependent Claim
17 words
A structure as in claim 1 wherein said simulation means comprises a plurality of primitive logic elements.
Claim 4
Dependent Claim
80 words
A structure as in claim 2 wherein said three state bus includes a plurality of three state elements and each three state element is represented in said simulation means by at least one primitive logic element in said plurality of primitive logic elements, and further wherein said at least one primitive logic element receives signals corresponding to the data input signal and the control input signal for the three state element represented by said at least one primitive logic element.
Claim 5
Dependent Claim
17 words
A structure as in claim 1 wherein said detecting means comprises a plurality of primitive logic elements.
Claim 6
Dependent Claim
64 words
A structure as in claim 4 wherein the three state bus includes n three state elements and further wherein said plurality of primitive logic elements comprise at least n primitive logic elements wherein each of said at least n primitive logic elements processes n signals where the n signals are associated with the n control input signals for the n element three state bus.
Claim 7
Independent Claim
124 words
A method for evaluating digital circuit data input and control input signals for a three state bus comprising the steps of: simulating digital logic signal propagation through said three state bus to generate an output signal for said three state bus for said data input and control input signals; detecting contentions on said three state bus and detecting floating of said three state bus by generating, in response to the control input signals, a signal having (i) a first constant predetermined value in the absence of contentions on and floating of said three state bus and (ii) a second constant predetermined value in the presence of each condition in the group of conditions consisting of contentions on and floating of said three state bus.
Claim 8
Independent Claim
124 words
A method for evaluating digital circuit data input and control input signals for a three state bus comprising the steps of: simulating digital logic signal propagation through said three state bus to generate an output signal for said three state bus for said data input and control input signals; detecting contentions on said three state bus and detecting floating of said three state bus by generating, in response to the control input signals, a signal having (i) a first constant predetermined value in the absence of contentions on and floating of said three state bus and (ii) a second constant predetermined value in the presence of each condition in the group of conditions consisting of contentions on and floating of said three state bus.
Claim 9
Dependent Claim
40 words
The method of claim 6 wherein the simulating step further comprises generating a logic network wherein the logic network receives said data input and control input signals and in response to these signals generates said three state bus output signal.
Claim 10
Dependent Claim
42 words
The method of claim 7 wherein the logic network generating step further comprises generating a plurality of primitive logic elements wherein each primitive logic element processes the control and data input signals for a three state element in said three state bus.
Claim 11
Dependent Claim
52 words
The method of claim 6 wherein the detecting contentions and floating step further comprises generating a logic network wherein the logic network receives said control input signals and generates, in turn, one of (i) said signal having a first constant predetermined value and (ii) said signal having said second constant predetermined value.
Claim 12
Dependent Claim
38 words
The method of claim 9 wherein the logic network generating step further comprises generating a plurality of primitive logic elements wherein each primitive logic element processes signals associated with the control input signals to the three state bus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-12 | 1998-06-13 | 1998-12-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-12 | 2002-06-13 | 2002-12-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-12 | 2006-06-13 | 2006-12-13 | $7700.00 | Window Closed / Lapsed |