US4945540A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gate circuit for bus signal lines
Assignee: Mitsubishi Electric Corp
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Filing: 1988-02-05
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Granted: 1990-07-31
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Expires: 2008-02-05
Abstract
Abstract A failure detecting gate circuit for bus signal lines. The gate circuit include gate elements connected to each bus line and controlled by control signal, and a processing unit which controls any one of the gate elements. The processing unit operates to switch the gate elements to an "ON" state when the control signals are supplied to the gate elements of each gate. The failure detecting circuit outputs an indication signal of a failure condition in the processing unit. This occurs when control signals are supplied, such that at least two gate elements are to be switched to the "ON" state simultaneously. The improvement of the present invention over previous devices is a multiplexer which outputs one of two signals indicating either a failure condition or a normal signal provided by the microcontroller.
Inventors
- 👤 Kouichi Kaneko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:57
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/221; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0763; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
204 words
In a bus gating circuit of the type for gating one of a plurality of input signals onto an internal bus line of a microcontroller, wherein the internal bus line provides for communication among a plurality of signal sources, with each input signal being connected to the internal bus line by a corresponding gate element that couples or isolates the corresponding input signal to or from the internal bus line depending on the active or inactive state of a control signal received by the gate element, a failure detection circuit for detecting an error condition in which two or more input signals are simultaneously coupled to the internal bus line, the failure detection circuit comprising: circuit means responsive to the control signal lines for generating an error signal when more than one of the control signal lines are active, the error signal providing an indication of a control signal error, wherein the input signals are unchanged by the error signal; and a multiplexer having a first input line carrying the error signal, a second input line carrying a normal signal from a microcontroller, a selection input line to choose between the inputs, and an output to carry the signal output of the selected input.
Claim 2
Dependent Claim
204 words
In a bus gating circuit of the type for gating one of a plurality of input signals onto an internal bus line of a microcontroller, wherein the internal bus line provides for communication among a plurality of signal sources, with each input signal being connected to the internal bus line by a corresponding gate element that couples or isolates the corresponding input signal to or from the internal bus line depending on the active or inactive state of a control signal received by the gate element, a failure detection circuit for detecting an error condition in which two or more input signals are simultaneously coupled to the internal bus line, the failure detection circuit comprising: circuit means responsive to the control signal lines for generating an error signal when more than one of the control signal lines are active, the error signal providing an indication of a control signal error, wherein the input signals are unchanged by the error signal; and a multiplexer having a first input line carrying the error signal, a second input line carrying a normal signal from a microcontroller, a selection input line to choose between the inputs, and an output to carry the signal output of the selected input.
Claim 3
Dependent Claim
34 words
A failure detecting circuit as claimed in claim 1 wherein the circuit means comprises a memory unit which provides a failure signal in case a plurality of control signals are supplied as address signals.
Claim 4
Dependent Claim
23 words
A bus gating circuit for internal bus lines as claimed in claim 1, wherein each gate element is composed of a tri-status gate.
Claim 5
Dependent Claim
23 words
A bus gating circuit for internal bus lines as claimed in claim 1, wherein each gate element is compsed of a transfer gate.
Claim 6
Dependent Claim
63 words
A bus gating circuit for internal bus lines as claimed in claim 2 wherein, the memory is composed of a ROM which stores a failure signal indicating that a failure condition exists at an address in the ROM, the failure signal being responsive to an address signal in the case that a plurality of control signals are address signals supplied to the ROM.
References Cited (Backward Citations)
US3860908A
Cited
JPS644148A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-30 | 1994-01-29 | 1994-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-30 | 1998-01-29 | 1998-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-30 | 2002-01-29 | 2002-07-31 | $7700.00 | Window Closed / Lapsed |