US3860908A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Rom multiple code conversion apparatus
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1974-02-04
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Granted: 1975-01-14
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Expires: 1994-02-04
Abstract
Abstract The code conversion apparatus uses a read-only memory, a parity checker and a plurality of logic gates to convert data characters from any one of several information codes to any one of several other information codes. The apparatus provides parity checking of each of the converted characters and also provides an illegalinput code flag when asked to convert an illegal input character.
Inventors
- 👤 Iii Lee N Stratton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 08:57
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; H; H03; H03M; H03M7/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
97 words
Multiple code conversion apparatus for use with a storage medium and a central processor, said apparatus comprising: a plurality of ROM code converters each having a plurality of signal input leads, a control lead, an illegal-input code flag lead and a plurality of signal output leads, each of said signal input leads being connected to said storage medium, each of said output leads being coupled to said processor, said input code flag lead being coupled to said processor; and a source of control signals, said source being connected to said control lead of each of said converters.
Claim 2
Dependent Claim
97 words
Multiple code conversion apparatus for use with a storage medium and a central processor, said apparatus comprising: a plurality of ROM code converters each having a plurality of signal input leads, a control lead, an illegal-input code flag lead and a plurality of signal output leads, each of said signal input leads being connected to said storage medium, each of said output leads being coupled to said processor, said input code flag lead being coupled to said processor; and a source of control signals, said source being connected to said control lead of each of said converters.
Claim 3
Dependent Claim
58 words
Multiple code conversion apparatus as defined in claim 1 including: a parity generator having a plurality of input leads and an output lead, each of said input lead of said generator being coupled to a corresponding one of said signal output leads of each of said converters, said output lead of said generator being connected to said processor.
Claim 4
Dependent Claim
225 words
Multiple code conversion apparatus for use with a storage medium and a central processor, said apparatus comprising: first and second ROM code converters each having a plurality of signal input leads, a control lead, an illegal-input code flag lead and a plurality of signal output leads, each of said input leads of said converters being connected to said storage medium; a source of control signals, said source being connected to said control lead of each of said converters; a plurality of logic gates each having first and second input leads and an output lead, said first input lead of each of said logic gates being connected to a corresponding one of said signal output leads of said first converter, said second input lead of each of said logic gates being connected to a corresponding one of said signal output leads of said second converter, said output lead of each of said logic gates being connected to said central processor; and a gating means having first and seCond input leads and an output lead, said first input lead of said gating means being connected to said illegal-input code flag lead of said first converter, said second input lead of said gating means being connected to said illegal-input code flag lead of said second converter, said output lead of said gating means being connected to said processor.
Claim 5
Dependent Claim
225 words
Multiple code conversion apparatus for use with a storage medium and a central processor, said apparatus comprising: first and second ROM code converters each having a plurality of signal input leads, a control lead, an illegal-input code flag lead and a plurality of signal output leads, each of said input leads of said converters being connected to said storage medium; a source of control signals, said source being connected to said control lead of each of said converters; a plurality of logic gates each having first and second input leads and an output lead, said first input lead of each of said logic gates being connected to a corresponding one of said signal output leads of said first converter, said second input lead of each of said logic gates being connected to a corresponding one of said signal output leads of said second converter, said output lead of each of said logic gates being connected to said central processor; and a gating means having first and seCond input leads and an output lead, said first input lead of said gating means being connected to said illegal-input code flag lead of said first converter, said second input lead of said gating means being connected to said illegal-input code flag lead of said second converter, said output lead of said gating means being connected to said processor.
Claim 6
Dependent Claim
59 words
Multiple code conversion apparatus as defined in claim 3 including: a parity generator having a plurality of input leads and an output lead, each of said input lead of said generator being coupled to a corresponding one of said signal output leads of each of said logic gates, said output lead of said generator being connected to said processor.
Claim 7
Dependent Claim
274 words
Multiple code conversion apparatus for use with a storage medium and a central processor, said apparatus comprising: first and second ROM code converters each having a plurality of signal input leads, a control lead, a parity output lead and a plurality of signal output leads, each of said input leads of said converters being connected to said storage medium; a source of control signals, said source being connected to said control lead of each of said converters; a plurality of logic gates each having first and second input leads and an output lead, said first input lead of each of said logic gates being connected to a corresponding one of said signal output leads of said first converter, said second input lead of each of said logic gates being connected to a corresponding one of said signal output leads of said second converter, said output lead of each of said logic gates being connected to said central processor; a gating means having first and second input leads and an output lead, said first input lead of said gating means being connected to said parity output lead of said first converter, said second input lead of said gating means being connected to said parity output lead of said second converter; a parity checker having a plurality of signal input leads, a parity lead and an output lead, said input leads of said checker each being connected to a corresponding one of said output lead of said logic gates, said output lead of said gating means being connected to said parity lead of said checker, said output lead of said checker being connected to said processor.
Claim 8
Dependent Claim
274 words
Multiple code conversion apparatus for use with a storage medium and a central processor, said apparatus comprising: first and second ROM code converters each having a plurality of signal input leads, a control lead, a parity output lead and a plurality of signal output leads, each of said input leads of said converters being connected to said storage medium; a source of control signals, said source being connected to said control lead of each of said converters; a plurality of logic gates each having first and second input leads and an output lead, said first input lead of each of said logic gates being connected to a corresponding one of said signal output leads of said first converter, said second input lead of each of said logic gates being connected to a corresponding one of said signal output leads of said second converter, said output lead of each of said logic gates being connected to said central processor; a gating means having first and second input leads and an output lead, said first input lead of said gating means being connected to said parity output lead of said first converter, said second input lead of said gating means being connected to said parity output lead of said second converter; a parity checker having a plurality of signal input leads, a parity lead and an output lead, said input leads of said checker each being connected to a corresponding one of said output lead of said logic gates, said output lead of said gating means being connected to said parity lead of said checker, said output lead of said checker being connected to said processor.
Claim 9
Dependent Claim
341 words
Multiple code conversion apparatus for use with a storage medium and a central processor, said apparatus comprising: first and second ROM code converters each having a plurality of signal input leads, a control lead, an illegal-input code flag lead, a parity output lead and a plurality of signal output leads, each of said input leads of said converters being connected to said storage medium; a source of control signals, said source being connected to said control lead of each of said converters; a plurality of logic gates each having first and second input leads and an output lead, said first input lead of each of said logic gates being connected to a corresponding one of said signal output leads of said first converter, said second input lead of each of said logic gates being connected to a corresponding one of said signal output leads of said second converter, said output lead of each of said logic gates being connected to said central processor; first and second gating means each having first and second input leads and an output lead, said first input lead of said first gating means being connected to said illegal-input code flag lead of said first converter, said second input lead of said first gating means being connected to said illegal-input code flag lead of said second converter, said output lead of said first gating means being connected to said processor, said first input lead of said second gating means being connected to said parity output lead of said first converter, said second input lead of said second gating means being connected to said parity output lead of said second converter; and a parity checker having a plurality of signal input leads, a parity lead and an output lead, said input leads of said checker each being connected to a corresponding one of said output leads of said logic gates, said output lead of said second gating means being connected to said parity lead of said checker, said output lead of said checker being connected to said processor.
Claim 10
Dependent Claim
341 words
Multiple code conversion apparatus for use with a storage medium and a central processor, said apparatus comprising: first and second ROM code converters each having a plurality of signal input leads, a control lead, an illegal-input code flag lead, a parity output lead and a plurality of signal output leads, each of said input leads of said converters being connected to said storage medium; a source of control signals, said source being connected to said control lead of each of said converters; a plurality of logic gates each having first and second input leads and an output lead, said first input lead of each of said logic gates being connected to a corresponding one of said signal output leads of said first converter, said second input lead of each of said logic gates being connected to a corresponding one of said signal output leads of said second converter, said output lead of each of said logic gates being connected to said central processor; first and second gating means each having first and second input leads and an output lead, said first input lead of said first gating means being connected to said illegal-input code flag lead of said first converter, said second input lead of said first gating means being connected to said illegal-input code flag lead of said second converter, said output lead of said first gating means being connected to said processor, said first input lead of said second gating means being connected to said parity output lead of said first converter, said second input lead of said second gating means being connected to said parity output lead of said second converter; and a parity checker having a plurality of signal input leads, a parity lead and an output lead, said input leads of said checker each being connected to a corresponding one of said output leads of said logic gates, said output lead of said second gating means being connected to said parity lead of said checker, said output lead of said checker being connected to said processor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-01-13 | 1978-07-15 | 1979-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-01-13 | 1982-07-15 | 1983-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-01-13 | 1986-07-15 | 1987-01-14 | $7700.00 | Window Closed / Lapsed |