US5497378A
Expired / Lapsed
US
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System and method for testing a circuit network having elements testable by different boundary scan standards
Assignee: GlobalFoundries Inc
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Filing: 1993-11-02
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Granted: 1996-03-05
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Expires: 2013-11-02
Abstract
Abstract Disclosed is a test method and system for boundary testing a circuit network. The network, made up of individual integrated circuit chips mounted on a printed circuit card or board, has at least one integrated circuit that is testable by IEEE 1149.1 Standard boundary testing, and at least one second integrated circuit that is testable by Level Sensitive Scan Design boundary testing but not by IEEE 1149.1 Standard boundary testing. The test system has a test access port interface with a test access port controller with Test Clock, Test Data In, Test Data Out, Test Mode Select, and Test Reset I/O. The test access port also has an instruction register, a bypass register, a test clock generator, and a Level Sensitive Scan Device boundary scan register.
Inventors
- 👤 Ismael Z. Amini
- 👤 William F. Heybruck
- 👤 Andres M. Molina
- 👤 Kimberly K. Van Vliet
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 04:48
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318558; G01R31/31701; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/46
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
169 words
A test fixture for boundary testing a circuit network having at least one first integrated circuit testable by IEEE 1149.1 Standard boundary testing, and at least one second integrated circuit testable by Level Sensitive Scan Design boundary testing but not by IEEE 1149.1 Standard boundary testing, and requiring three clocks for testing; said test fixture comprising a test access port interface comprising: a. a test access port controller with Test Clock, Test Data In, Test Data Out, Test Mode Select, and Test Reset I/O means; b. an instruction register; c. a bypass register; d. a test clock; and e. a Level Sensitive Scan Device boundary scan register having the control input signals: i. LSSD clocks CLK A, CLK B, and CLK C; ii. boundary scan output BSCO controlling boundary scan cells on the Level Sensitive Scan Device integrated circuit chip associated with drivers; iii. boundary scan input BSCI controlling boundary scan cells on the Level Sensitive Scan Device integrated circuit chip associated with receivers; and iv. data inhibit, DI1.
Claim 2
Dependent Claim
169 words
A test fixture for boundary testing a circuit network having at least one first integrated circuit testable by IEEE 1149.1 Standard boundary testing, and at least one second integrated circuit testable by Level Sensitive Scan Design boundary testing but not by IEEE 1149.1 Standard boundary testing, and requiring three clocks for testing; said test fixture comprising a test access port interface comprising: a. a test access port controller with Test Clock, Test Data In, Test Data Out, Test Mode Select, and Test Reset I/O means; b. an instruction register; c. a bypass register; d. a test clock; and e. a Level Sensitive Scan Device boundary scan register having the control input signals: i. LSSD clocks CLK A, CLK B, and CLK C; ii. boundary scan output BSCO controlling boundary scan cells on the Level Sensitive Scan Device integrated circuit chip associated with drivers; iii. boundary scan input BSCI controlling boundary scan cells on the Level Sensitive Scan Device integrated circuit chip associated with receivers; and iv. data inhibit, DI1.
Claim 3
Dependent Claim
37 words
The test fixture of claim 1 wherein the Level Sensitive Scan Device Boundary Scan Register controls BSCO and BSCI when Test Access Port control lines Shift Data Register SHIFTDR, and Boundary Scan Register Select BSSEL are high.
Claim 4
Dependent Claim
37 words
The test fixture of claim 1 wherein the Level Sensitive Scan Device Boundary Scan Register controls BSCO and BSCI when Test Access Port control lines Update Data Register UPDATDR, and Boundary Scan Register Select BSSEL are high.
Claim 5
Dependent Claim
52 words
The test fixture of claim 1 wherein the Data Inhibit Signal DI1 is high and data is sent out to the circuit network from the Level Sensitive Scan Device integrated circuit chip when Boundary Scan Select BSSEL and one of Update Data Register, select Data Register, or Capture Data Register is high.
Claim 6
Dependent Claim
42 words
The test fixture of claim 1 wherein the Data Inhibit DI1 is connected to the inhibit pins of the Level Sensitive Scan Device whereby when DI1 is low no signals are transmitted over the circuit network from non-selected second integrated circuit chips.
Claim 7
Dependent Claim
58 words
The test fixture of claim 1 wherein the Data Inhibit DI1 is connected to the inhibit pins of the Level Sensitive Scan Device whereby when DI1 is high the Level Sensitive Scan Device chip drivers are enabled and Level Sensitive Scan Device boundary scan cell contents are transmitted over the circuit network from selected second integrated circuit chips.
Claim 8
Independent Claim
222 words
A method for boundary testing a circuit network having at least one first integrated circuit testable by IEEE 1149.1 Standard boundary testing, and at least one second integrated circuit testable by Level Sensitive Scan Design boundary testing but not by IEEE 1149.1 Standard boundary testing, and requiring three clocks for testing; said method comprising inserting said circuit network in a test fixture comprising a test access port interface comprising: a. a test access port controller with Test Clock, Test Data In, Test Data Out, Test Mode Select, and Test Reset I/O means; b. an instruction register; c. a bypass register; d. a test clock generator; and e. a Level Sensitive Scan Device boundary scan register having the control input signals: i. LSSD clocks CLK A, CLK B, and CLK C; ii. boundary scan output BSCO controlling boundary scan cells on the Level Sensitive Scan Device integrated circuit chip associated with drivers; iii. boundary scan input BSCI controlling boundary scan cells on the Level Sensitive Scan Device integrated circuit chip associated with receivers; and iv. data inhibit, DI1; and applying test signals to the IEEE 1149.1 Standard first integrated circuit through the test access port controller, and applying test signals to the Level Sensitive Scan Device second integrated circuit through the test access port and the Level Sensitive Scan Device boundary scan register.
Claim 9
Independent Claim
222 words
A method for boundary testing a circuit network having at least one first integrated circuit testable by IEEE 1149.1 Standard boundary testing, and at least one second integrated circuit testable by Level Sensitive Scan Design boundary testing but not by IEEE 1149.1 Standard boundary testing, and requiring three clocks for testing; said method comprising inserting said circuit network in a test fixture comprising a test access port interface comprising: a. a test access port controller with Test Clock, Test Data In, Test Data Out, Test Mode Select, and Test Reset I/O means; b. an instruction register; c. a bypass register; d. a test clock generator; and e. a Level Sensitive Scan Device boundary scan register having the control input signals: i. LSSD clocks CLK A, CLK B, and CLK C; ii. boundary scan output BSCO controlling boundary scan cells on the Level Sensitive Scan Device integrated circuit chip associated with drivers; iii. boundary scan input BSCI controlling boundary scan cells on the Level Sensitive Scan Device integrated circuit chip associated with receivers; and iv. data inhibit, DI1; and applying test signals to the IEEE 1149.1 Standard first integrated circuit through the test access port controller, and applying test signals to the Level Sensitive Scan Device second integrated circuit through the test access port and the Level Sensitive Scan Device boundary scan register.
Claim 10
Dependent Claim
36 words
The method of claim 7 wherein the Level Sensitive Scan Device Boundary Scan Register controls BSCO and BSCI when Test Access Port control lines Shift Data Register SHIFTDR, and Boundary Scan Register Select BSSEL are high.
Claim 11
Dependent Claim
36 words
The method of claim 7 wherein the Level Sensitive Scan Device Boundary Scan Register controls BSCO and BSCI when Test Access Port control lines Update Data Register UPDATDR, and Boundary Scan Register Select BSSEL are high.
Claim 12
Dependent Claim
51 words
The method of claim 7 wherein the Data Inhibit Signal DI1 is high and data is sent out to the circuit network from the Level Sensitive Scan Device integrated circuit chip when Boundary Scan Select BSSEL and one of Update Data Register, Select Data Register, or Capture Data Register is high.
Claim 13
Dependent Claim
41 words
The method of claim 7 herein the Data Inhibit DI1 is connected to the inhibit pins of the Level Sensitive Scan Device whereby when DI1 is low no signals are transmitted over the circuit network from non-selected second integrated circuit chips.
Claim 14
Dependent Claim
57 words
The method of claim 7 wherein the Data Inhibit DI1 is connected to the inhibit pins of the Level Sensitive Scan Device whereby when DI1 is high the Level Sensitive Scan Device chip drivers ate enabled and Level Sensitive Scan Device boundary scan cell contents are transmitted over the circuit network from selected second integrated circuit chips.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-05 | 1999-09-04 | 2000-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-05 | 2003-09-04 | 2004-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-05 | 2007-09-04 | 2008-03-05 | $7700.00 | Window Closed / Lapsed |