System and method for testing a circuit network having elements testable by different boundary scan standards

Claim 1

A test fixture for boundary testing a circuit network having at least one first integrated circuit testable by IEEE 1149.1 Standard boundary testing, and at least one second integrated circuit testable by Level Sensitive Scan Design boundary testing but not by IEEE 1149.1 Standard boundary testing, and requiring three clocks for testing; said test fixture comprising a test access port interface comprising: a. a test access port controller with Test Clock, Test Data In, Test Data Out, Test Mode Select, and Test Reset I/O means; b. an instruction register; c. a bypass register; d. a test clock; and e. a Level Sensitive Scan Device boundary scan register having the control input signals: i. LSSD clocks CLK A, CLK B, and CLK C; ii. boundary scan output BSCO controlling boundary scan cells on the Level Sensitive Scan Device integrated circuit chip associated with drivers; iii. boundary scan input BSCI controlling boundary scan cells on the Level Sensitive Scan Device integrated circuit chip associated with receivers; and iv. data inhibit, DI1.

Claim 8

A method for boundary testing a circuit network having at least one first integrated circuit testable by IEEE 1149.1 Standard boundary testing, and at least one second integrated circuit testable by Level Sensitive Scan Design boundary testing but not by IEEE 1149.1 Standard boundary testing, and requiring three clocks for testing; said method comprising inserting said circuit network in a test fixture comprising a test access port interface comprising: a. a test access port controller with Test Clock, Test Data In, Test Data Out, Test Mode Select, and Test Reset I/O means; b. an instruction register; c. a bypass register; d. a test clock generator; and e. a Level Sensitive Scan Device boundary scan register having the control input signals: i. LSSD clocks CLK A, CLK B, and CLK C; ii. boundary scan output BSCO controlling boundary scan cells on the Level Sensitive Scan Device integrated circuit chip associated with drivers; iii. boundary scan input BSCI controlling boundary scan cells on the Level Sensitive Scan Device integrated circuit chip associated with receivers; and iv. data inhibit, DI1; and applying test signals to the IEEE 1149.1 Standard first integrated circuit through the test access port controller, and applying test signals to the Level Sensitive Scan Device second integrated circuit through the test access port and the Level Sensitive Scan Device boundary scan register.

Claim 9

A method for boundary testing a circuit network having at least one first integrated circuit testable by IEEE 1149.1 Standard boundary testing, and at least one second integrated circuit testable by Level Sensitive Scan Design boundary testing but not by IEEE 1149.1 Standard boundary testing, and requiring three clocks for testing; said method comprising inserting said circuit network in a test fixture comprising a test access port interface comprising: a. a test access port controller with Test Clock, Test Data In, Test Data Out, Test Mode Select, and Test Reset I/O means; b. an instruction register; c. a bypass register; d. a test clock generator; and e. a Level Sensitive Scan Device boundary scan register having the control input signals: i. LSSD clocks CLK A, CLK B, and CLK C; ii. boundary scan output BSCO controlling boundary scan cells on the Level Sensitive Scan Device integrated circuit chip associated with drivers; iii. boundary scan input BSCI controlling boundary scan cells on the Level Sensitive Scan Device integrated circuit chip associated with receivers; and iv. data inhibit, DI1; and applying test signals to the IEEE 1149.1 Standard first integrated circuit through the test access port controller, and applying test signals to the Level Sensitive Scan Device second integrated circuit through the test access port and the Level Sensitive Scan Device boundary scan register.