EP0604032B1
Expired / Lapsed
EP
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Scan testing of integrated circuits
Assignee: Advanced Micro Devices Inc
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Filing: 1993-11-30
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Granted: 1998-09-23
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Expires: 2013-11-30
Abstract
Abstract A test circuit and test technique for scan testing integrated circuits (95) includes scan cells (100, 110, 120) or capture scan elements arranged in a pseudo master slave configuration. The testing technique utilizes first independent scan cell (100, 110, 120) as a master stage and a second independent scan cell (100, 110, 120) as a slave stage for propagating data through the IC. The test circuit and test techniques are highly advantageous because of minimal structural overhead. However, the scan cells (100, 110, 120) must be loaded twice to recover the test data because half the test data is lost when the data is propagated through the IC. The shift register inputs (109, 119, 199) of one scan cell (100, 110, 120) are generally coupled to shift register outputs (108, 118, 128) of other scan cells. Each scan cell (100, 110, 120) generally only includes one latch element (131).
Inventors
- 👤 Gopi Ganapathy
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 07:03
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
349 words
A method for testing an integrated circuit (95), the integrated circuit including
an array of scan latches as defined in claim 6, the array having a first scan latch (100) controlled by a first
test clock signal (TCLK, T0), a second scan latch (110) controlled by a second test
clock signal (TCLK, T1), and a third scan latch (120) controlled by the first test clock
signal (TCLK, T0), each said scan latch consisting essentially of a single latch storage
element (130), the second scan latch (110) being coupled between the first (100) and
third (120) scan latches, the method comprising the steps of: loading a data pattern comprised of a first bit, a second bit and a third bit, the
first and third bits being loaded into the first (100) and third (120) scan
latches, respectively, and the second bit being loaded into the second scan
latch (110); applying the first test clock signal (TCLK, T0) to the first and third scan
latches so that the first scan latch (100) stores the second bit and the first and
third bits are destroyed ; retrieving the second bit from the first scan latch (100); reloading the data pattern comprised of the first bit, the second bit and the
third bit, the first and third bits being loaded into the first (100) and third
(120) scan latches respectively, and the second bit being loaded into the second
scan latch (110); applying the second test clock signal (TCLK, T1) to the second scan latch
(110) so that the second scan latch stores the third bit and the second bit is
destroyed; applying the first test clock signal (TCLK, T0) to the first (100) and third
(120) scan latches so that the first scan latch (100) stores the third bit and the
first bit is eliminated; and retrieving the third bit from the first scan latch; whereby said method steps operate the array of scan latches as a pseudo master slave scan
latch array utilising fewer transistors than an array in which each scan latch
has a master stage and a slave stage.
Claim 2
Dependent Claim
21 words
The method of claim 1, further comprising the step of: comparing the second and third bit to a test data pattern.
Claim 3
Dependent Claim
30 words
The method of claim 1 or claim 2 further comprising the step of retrieving the
first bit from the first scan latch (100) before providing the first test clock signal.
Claim 4
Dependent Claim
36 words
The method of claim 3 wherein the integrated circuit further comprises an
external pin (XS0) coupled to the first scan latch (100) and the steps of retrieving
includes monitoring the signal on the external pin (XS0).
Claim 5
Independent Claim
31 words
The method of any one of claims 1 to 4 wherein the scan latches operate as
independent sequential elements when the integrated circuit is in a normal system
mode of operation.
Claim 6
Dependent Claim
372 words
An integrated circuit including an array of scan latches, the array comprising: a first scan latch (100) consisting essentially of a single latch storage element
(100, 130), the first scan latch having a first test clock input (102), a first shift
register output (108), and a first shift register input (109), the first latch
storage element (100, 130) being coupled between the first shift register input
(109) and the first shift register output (108); a second scan latch (110) consisting essentially of a single latch storage
element (110, 130) and having a second test clock input (112), a second shift
register output (118), and a second shift register input (119), the second latch
storage element (110, 130) being coupled between the second shift register
input (119) and the second shift register output (118); and a third scan latch (120) consisting essentially of a single latch storage element
(120, 130) and having a third test clock input (122), a third shift register
output (128), and a third shift register input (129), the third latch storage
element (120, 130) being coupled between the third shift register input (129)
and the third shift register output; wherein the first to third scan latches each includes a
capture data input (104,114,124) and a capture clock input (106,116,126) and wherein the first test clock input (102) is coupled to the third test clock input
(122) wherein the first shift register input (109) is coupled to the second shift
register output (118) and the third shift register output (128) is coupled to the
second shift register input (119) wherein first data stored in the third latch
storage element (120, 130) is propagated to the first latch storage element
(100, 130) by providing a first shift signal (TCLK, T1) at the second clock
input (112) followed by a second shift signal (TCLK, T0) at the first and third
clock inputs (102, 122), and wherein second data stored in the second latch
storage element (110, 130) is destroyed as the first data is propagated; whereby the scan latches are configured and arranged to operate as a pseudo
master slave scan latch array utilising fewer transistors than an array in which
each scan latch has a master stage and a slave stage.
Claim 7
Dependent Claim
56 words
The integrated circuit of claim 6
wherein the first data is loaded in the third latch storage element (120, 130) by providing
an initial shift signal (TCLK, T0) at the first and
third clock inputs (102,122) and wherein data
originally stored in the first and third storage
elements is destroyed as said first data is loaded.
References Cited (Backward Citations)
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