A high impedance technique for testing interconnections in digital systems

Claim 2

The cell of claim 1 for use in a circuit device having a plurality of input/output pins (30; 40) wherein each transmit scan cell (10) is associated with a device output pin (30), characterized by - said scan flip-flop (19) selectively storing a scan input; - said three-state buffer (11) being responsive to a test signal for providing a buffered output signal on an associated device output pin (30); and - said control logic being provided for (a) enabling said three-state buffer (11) and providing the input test signal input to the three-state buffer (11) at a first logical state so that the output of said three-state buffer (11) is at the first logical state; (b) disabling said three-state buffer (11) to the high impedance state while a scan input is scanned into said scan flip-flop (19); (c) providing the input test signal to said three-state buffer (11) at a second logical state after the scan input for the scan flip-flop (19) has been scanned in; and (d) enabling said three-state buffer (11) if the scan input scanned into said scan register (19) is of the second logical state so as to cause the output of the three-state buffer (11) to be at the second logical state, whereby said three-state buffer (11) remains in the high impedance state if the scan input scanned into said scan register (19) is of the first logical state.

Claim 3

A receive scan cell (20) for a circuit device having input/output pins (30; 40) for interconnection with other circuit devices, characterized by: - an input buffer (51); - holding means (53) connected to the input of said input buffer (51) for allowing the input to the input buffer (51) to be driven at a first or second logical state, and for changing the input to said input buffer (51) to a predetermined one of the first and second logical states if the connection to the input to said input buffer (51) is an open connection or a high impedance connection; and - a scan flip-flop (57) for controllably storing the output of said input buffer (11).

Claim 4

A boundary scan cell (10; 20) characterized by: - A transmit scan flip-flop (19) for storing a scan input; - a three-state buffer (11) responsive to an input signal for providing a buffered output signal on a device output pin (30); - an input buffer (51) having an input connected to a device input pin (40); - holding means (53) connected to the input of said input buffer (51) for allowing the input of said input buffer (51) to be driven to a first logical state or a second logical state, and for changing the input to said input buffer (51) to the first logical state if such input is an open connection or a high impedance connection, said holding means (53) allowing the input to the buffer (51) to change to the second logical state when driven to the second logical state; and - a receive scan flip-flop (57) for controllably storing the output of said input buffer (51); - wherein the input of said input buffer (51) is intended to be interconnected with the output of said three-state buffer (11), and the status of such interconnection can be tested by (a) enabling said three-state buffer (11) and providing the test input to said three-state buffer (11) at a first logical state so that the output of said three-state buffer (11) is at a first logical state, (b) disabling said three-state buffer (11) to the high impedance state while a scan input is canned into said transmit scan flip-flop (19), (c) providing the test input to said three-state buffer (11) at the second logical state after the scan input for the transmit scan flip-flop (19) has been scanned in, and (d) enabling said three-state buffer (11) if the scan input scanned into said scan register is at the second logical state so as to cause the output of the three-state buffer to be at the second logical state, whereby said three-state buffer (11) remains in the high impedance state if the scan input is of the first logical state.

Claim 5

A boundary scan circuit cell (10; 20) for use in a scan chain in a device having a plurality of input/output (I/O) pins (30; 40) wherein each scan cell (10; 20) is associated with a specific I/O pin (30; 40), characterized by: - input buffering means (51) responsive to signals applied to the associated I/O pin (40) for providing a buffered input signal; - input storage means (57) responsive to said buffered input signal and to a scan input for controllably storing the buffered input signal or a scan input signal; - a three-state output buffer (11) responsive to a test input for providing a buffered output signal on the associated I/O pin (30) of the circuit device; and - control logic means responsive to said scan flip-flop and to the test input for selectively enabling or disabling said three-state buffer (11).