Integrated circuit device

Claim 1

An integrated circuit device comprising: a package; a plurality of pins extending from the package for providing input and output pathways for signals to and from the device; a substrate housed within the package; and a plurality of circuit elements located on the substrate and connected to one another and to the pins, certain ones of the circuit elements and correponding ones of the pins having functionally critical timing dependencies; characterised in that the device further includes bidirectional driver/receiver elements interposed between corresponding pins and the certain ones of the circuit elements for permitting normal functional passage of signals in one direction through the corresponding pins and for permitting testing of connections between the device and conductive pathways of a printed circuit board by passage of signals in the opposite direction through the corresponding pins in response to incircuit test control signals.

Claim 7

A method of preparing an integrated circuit device for testing for proper connection with a printed circuit device in which the integrated circuit device is mounted comprising the steps of: providing a substrate; forming on said substrate a plurality of connected circuit elements operatively associated with one another for performing determinable functions; forming certain ones of said plurality of circuit elements to have functionally critical timing dependencies and to include bi-directional driver/receiver elements interposed between a said certain ones and others of said certain ones of said circuit elements, said driver/receiver elements being available for incircuit test control signals enabling and disabling said driver/receiver elements for permitting normal functional passage of signals in one direction and for permitting testing by passage of signals in an opposite direction; enclosing said substrate and said circuit elements in a package having a plurality of pin connectors; and connecting pins with corresponding circuit elements for normal functional passage of signals in one direction and for permitting testing by passage of signals in an opposite direction.

Claim 8

A method of testing a printed circuit device for proper connection of the pins provided on an integrated circuit device mounted on the printed circuit device and comprising the steps of: providing an integrated circuit device having: a package; a plurality of pins extending from the package for providing input and output pathways for signals exchanged with the integrated circuit device; a substrate housed within the package; and a plurality of connected circuit elements operatively associated with the substrate and with one another for performing determinable functions, the circuit elements being operatively associated with the pins for exchange of signals therethrough, certain ones of the plurality of circuit elements and corresponding ones of the plurality of pins having functionally critical timing dependencies, and the certain ones of the circuit elements including bi-directional driver/receiver elements interposed between a corresponding pin and others of the certain ones of the circuit elements, the driver/receiver elements being available for incircuit test control signals applied through the pins for enabling and disabling the driver/receiver elements for permitting normal functional passage of signals in one direction through an associated pin and for permitting testing by passage of signals in an opposite direction through an associated pin; mounting the integrated circuit on a printed circuit board having a plurality of conductive pathways supported by said board for connection to the integrated circuit device; connecting the pins with the conductive pathways; testing the connections between the pins and the pathways by applying test control signals through the conductive pathways for disabling the driver/receiver elements and permitting testing by passage of signals through the associated pin in a direction opposite to normal functional passage of signals through the associated pin; and removing the test control signals for enabling the driver/receiver elements to permit normal functional passage of signals through an associated pin.

Claim 9

A method of testing a personal computer planar board for proper connection of the pins provided on an integrated circuit device mounted on the board and comprising the steps of: providing an integrated circuit device having: a package; a plurality of pins extending from the package for providing input and output pathways for signals exchanged with the integrated circuit device; a substrate housed within the package; and a plurality of connected circuit elements operatively associated with the substrate and with one another for performing determinable functions, the circuit elements being operatively associated with the pins for exchange of signals therethrough, certain ones of the plurality of circuit elements and corresponding ones of the plurality of pins having functionally critical timing dependencies, and the certain ones of the circuit elements including bi-directional driver/receiver elements interposed between a corresponding pin and others of the certain ones of the circuit elements, the driver/receiver elements being available for incircuit test control signals applied through the pins for enabling and disabling the driver/receiver elements for permitting normal functional passage of signals in one direction through an associated pin and for permitting testing by passage of signals in an opposite direction through an associated pin; mounting the integrated circuit on a planar board having a plurality of conductive pathways supported by said board for connection to the integrated circuit device; connecting the pins with the conductive pathways; testing the connections between the pins and the pathways by applying test control signals through the conductive pathways for disabling the driver/receiver elements and permitting testing by passage of signals through the associated pin in a direction opposite to normal functional passage of signals through the associated pin; and removing the test control signals for enabling the driver/receiver elements to permit normal functional passage of signals through an associated pin.