Dimm pair with data memory and state memory

Claim 2

A dual in-line memory module (DIMM) memory pair comprising: (a) a first DIMM including i) a first data memory having first and second memory bank portions for storing data, and ii) a first state memory configured to store state information corresponding to data stored in a first memory bank; and (b) a second DIMM including i) a second data memory having third and fourth memory bank portions for storing data, and ii) a second state memory configured to store state information corresponding to data stored in a second memory bank, wherein said first memory bank is formed from said fast memory bank portion and said third memory bank portion, and wherein said second memory bank is formed from said second memory bank portion and said fourth memory bank portion.

Claim 3

The DIMM memory pair of claim 1, wherein said first DIMM further comprises first means for permitting said first data memory and said first state memory to be separately accessed, and wherein said second DIMM further comprises second means for permitting said second data memory and said second state memory to be separately accessed.

Claim 4

The DIMM memory pair of claim 2, wherein each of said first means and said second means comprises a connector.

Claim 5

The DIMM memory pair of claim 3, wherein each connector comprises a plurality of pads, said pads including a first group of address pads, a second group of address pads, a first group of data pads, and a second group of data pads.

Claim 6

The DIMM memory pair of claim 4, wherein each plurality of pads for each connector has the following arrangement: said first group of data pads and said first group of address pads are electrically coupled to a corresponding one of said first data memory and said second data memory; and said second group of data pads and said second group of address pads are electrically coupled to a corresponding one of said first state memory and said second state memory, wherein said arrangement permits independent addressing of said first data memory and said first state memory of said first DIMM and independent addressing of said second data memory and said second state memory of said second DIMM.

Claim 7

The DIMM memory pair of claim 4, wherein each plurality of pads for each connector further comprises first control pads for said corresponding one of said first data memory and said second data memory and second control pads for said corresponding one of said first state memory and said second state memory.

Claim 8

The DIMM memory pair of claim 6, wherein said first control pads for each connector include row access strobe pads, column access strobe pads, chip enable pads and write enable pads, and wherein said second control pads include row access strobe pads, column access strobe pads, chip enable pads and write enable pads.

Claim 9

The DIMM memory pair of claim 5, wherein said first group of address pads includes at least 12 pads.

Claim 10

The DIMM memory pair of claim 8, wherein said second group of address pads includes at least 12 pads.

Claim 11

The DIMM memory pair of claim 9, wherein said first group of data pads includes 72 pads.

Claim 12

The DIMM memory pair of claim 10, wherein said second group of data pads includes 16 pads.

Claim 13

The DIMM memory pair of claim 4, wherein each connector is an edge connector having two sides and 122 pads per side.

Claim 14

The DIMM memory pair of claim 1, wherein said first DIMM further comprises a phase locked loop clock driver coupled to said first data memory and said first state memory.

Claim 15

The DIMM memory pair of claim 1, wherein said second DIMM further comprises a phase locked loop clock driver coupled to said second data memory and said second state memory.

Claim 16

The DIMM memory pair of claim 1, wherein each of said first memory bank and said second memory bank is logically organized into memory blocks, and wherein said state information includes cache coherence information for data stored in a group of said memory blocks.

Claim 17

The DIMM memory pair of claim 1, wherein each of said first data memory and said second data memory comprises a plurality of synchronous dynamic random access memory (SDRAM) chips.

Claim 18

The DIMM memory pair of claim 16, wherein each of said first state memory and said second state memory comprises at least one synchronous dynamic random access memory (SDRAM) chip.

Claim 19

The DIMM memory pair of claim 17, wherein each of said first memory bank portion, said second memory bank portion, said third memory bank portion, and said fourth memory bank portion comprises nine (9) SDRAM chips, each of said nine SDRAM chips being two megabits (2 M) deep and eight (8) bits wide.

Claim 20

The DIMM memory pair of claim 18, wherein each of said first state memory and said second state memory comprises a one megabit (1 M) deep by sixteen (16) bit wide SDRAM chip.

Claim 21

The DIMM memory pair of claim 19, wherein said first DIMM comprises a first printed circuit board having an edge connector for electrical communication with said first DIMM, said first memory bank portion having said nine SDRAM chips mounted on a first side of said first printed circuit board, said second memory bank portion having said nine SDRAM chips mounted on a second side of said first printed circuit board, and said first state memory having said one SDRAM chip mounted on said first side of said first printed circuit board; and said second DIMM comprises a second printed circuit board having an edge connector for electrical communication with said second DIMM, said third memory bank portion having said nine SDRAM chips mounted on a first side of said second printed circuit board, said fourth memory bank portion having said nine SDRAM chips mounted on a second side of said second printed circuit board, and said second state memory having said one SDRAM chip mounted on said first side of said second printed circuit board.

Claim 22

The DIMM memory pair of claim 17, wherein each of said first memory bank portion, said second memory bank portion, said third memory bank portion, and said fourth memory bank portion comprises eighteen (18) SDRAM chips, each of said eighteen SDRAM chips being four megabits (4 M) deep and four (4) bits wide.

Claim 23

The DIMM memory pair of claim 21, wherein each of said first state memory and said second state memory comprises two (2) SDRAM chips, each of said two SDRAM chips being two megabit (2 M) deep by eight (8) bit wide.

Claim 24

The DIMM memory pair of claim 22, wherein said first DIMM comprises a first printed circuit board having an edge connector for electrical communication with said first DIMM, and a second printed circuit board mounted in a parallel, piggy back configuration on said first printed circuit board, said first memory bank portion having nine of said eighteen SDRAM chips mounted on a first side of said first printed circuit board and the other nine of said eighteen SDRAM chips mounted on a first side of said second printed circuit board, said second memory bank portion having nine of said eighteen SDRAM chips mounted on a second side of said first printed circuit board and the other nine of said eighteen SDRAM chips of said memory bank portion mounted on a second side of said second printed circuit board, and said first state memory having one of said two SDRAM chips mounted on each side of said first printed circuit board; and said second DIMM comprises a third printed circuit board having an edge connector for electrical communication with said second DIMM, and a fourth printed circuit board mounted in a parallel, piggy back configuration on said third printed circuit board, said third memory bank portion having nine of said eighteen SDRAM chips mounted on a first side of said third printed circuit board and the other nine of said eighteen SDRAM chips mounted on a first side of said fourth printed circuit board, said fourth memory bank portion having nine of said eighteen SDRAM chips mounted on a second side of said third printed circuit board and the other nine of said eighteen SDRAM chips of said memory bank portion mounted on a second side of said fourth printed circuit board, and said second state memory having one of said two SDRAM chips mounted on each side of said third printed circuit board.

Claim 25

The DIMM memory pair of claim 1, wherein each of said first state memory and said second state memory comprises at least one synchronous dynamic random access memory (SDRAM) chip.

Claim 26

The DIMM memory pair of claim 1, wherein said first memory bank portion, said second memory bank portion, said third memory bank portion, and said fourth memory bank portion each comprise nine (9) SDRAM chips, each of said nine SDRAM chips being two megabits (2 M) deep and eight (8) bits wide.

Claim 27

The DIMM memory pair of claim 1, wherein said first state memory and said second state memory each comprise a one megabit (1 M) deep by sixteen (16) bit wide SDRAM chip.

Claim 28

The DIMM memory pair of claim 1, wherein said first DIMM comprises a first printed circuit board having an edge connector for electrical communication with said first DIMM, said first memory bank portion including at least nine SDRAM chips mounted on a first side of said first printed circuit board, said second memory bank portion including at least nine SDRAM chips mounted on a second side of said first printed circuit board, and said first state memory including at least one SDRAM chip mounted on said first side of said first printed circuit board; and said second DIMM comprises a second printed circuit board having an edge connector for electrical communication with said second DIMM, said third memory bank portion including at least nine SDRAM chips mounted on a first side of said second printed circuit board, said fourth memory bank portion including at least nine SDRAM chips mounted on a second side of said second printed circuit board, and said second state memory including at least one SDRAM chip mounted on said first side of said second printed circuit board.

Claim 29

The DIMM memory pair of claim 1, wherein said first memory bank portion, said second memory bank portion, said third memory bank portion, and said fourth memory bank portion each comprise eighteen (18) SDRAM chips, each of said eighteen SDRAM chips being four megabits (4 M) deep and four (4) bits wide.

Claim 30

The DIMM memory pair of claim 1, wherein said first state memory and said second state memory each comprise two (2) SDRAM chips, each of said two SDRAM chips being two megabit (2 M) deep by eight (8) bit wide.

Claim 31

The DIMM memory pair of claim 1, wherein said first DIMM comprises a first printed circuit board having an edge connector for electrical communication with said first DIMM, and a second printed circuit board mounted in a parallel, piggy back configuration on said first printed circuit board, said first memory bank portion including at least nine SDRAM chips mounted on a first side of said first printed circuit board and at least nine SDRAM chips mounted on a first side of said second printed circuit board, said second memory bank portion including nine SDRAM chips mounted on a second side of said first printed circuit board and at least nine SDRAM chips mounted on a second side of said second printed circuit board, and said first state memory including at least one SDRAM chip mounted on each side of said first printed circuit board; and said second DIMM comprises a third printed circuit board having an edge connector for electrical communication with said second DIMM, and a fourth printed circuit board mounted in a parallel, piggy back configuration on said third printed circuit board, said third memory bank portion including at least nine SDRAM chips mounted on a first side of said third printed circuit board and at least nine SDRAM chips mounted on a first side of said fourth printed circuit board, said fourth memory bank portion including at least nine SDRAM chips mounted on a second side of said third printed circuit board and at least nine of said eighteen SDRAM chips of said memory bank portion mounted on a second side of said fourth printed circuit board, and said second state memory including at least one SDRAM chip mounted on each side of said third printed circuit board.

Claim 32

The DIMM memory pair of claim 1, wherein said first DIMM further comprises first means for permitting said first data memory and said first state memory to be separately accessed.

Claim 33

The DIMM memory pair of claim 31, wherein said first means comprises a connector.

Claim 34

The DIMM memory pair of claim 32, wherein said connector comprises a plurality of pads, said pads including a first group of address pads, a second group of address pads, a first group of data pads, and a second group of data pads.

Claim 35

The DIMM memory pair of claim 32, wherein said connector comprises the following arrangement: a first group of data pads and a first group of address pads electrically coupled to said first data memory; and a second group of data pads and a second group of address pads electrically coupled to said first state memory, wherein said arrangement permits independent addressing of said first data memory and said first state memory of said first DIMM.