US4610000A
Expired / Lapsed
US
⏱️ 0.0 years remaining
ROM/RAM/ROM patch memory circuit
Assignee: STMicroelectronics lnc USA
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Filing: 1984-10-23
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Granted: 1986-09-02
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Expires: 2004-10-23
Abstract
Abstract An integrated circuit contains ROM, ROM patch and RAM memories on a common substrate with a standard pinout. The ROM and RAM fill the address space allowed by the address pins. Control of the patch memory without the use of special control pins is accomplished by writing to a ROM address with the standard control pins set for a RAM write. Various control functions are made of a series of standard-cycle read and write operations.
Inventors
- 👤 Robert D. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:47
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/005; G06; G06F; G06F1/00; G06F1/22; G06F12/00; G06F12/02; G06F12/06; G06F12/0638
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
252 words
An integrated circuit memory system comprising: a read-only memory; a patch-memory on a substrate common to said read-only memory for patching predetermined blocks of said read-only memory; an input address bus connected to said read-only memory and said patch memory; a control logic unit comprising decoding circuitry for enabling a predetermined portion of said patch memory in response to a predetermined address on said address bus; and output means responsive to said predetermined address for connecting data from either said read-only memory or said patch memory to at least one input/output terminal, characterized in that: said memory system further comprises a nonvolatile random-access memory, sharing a common address space with said read-only memory, said random access memory and said read-only memory combining to fill said address space; each of said random-access memory and said patch-memory comprises an array of volatile memory cells; said random-access memory is controlled by memory overhead circuitry, having a write control pin, for reading data out from and writing data into that portion of said array of volatile memory cells within a random-access portion of said common address space; said patch-memory and said random-access memory are both connected to a voltage-maintenance circuit containing circuit means responsive to a power supply voltage and to at least one battery voltage for maintaining data in said patch-memory and said random-access memory when said power supply voltage is below a predetermined threshold, whereby data in said array of volatile memory cells is preserved during periods when said power supply voltage is low.
Claim 2
Dependent Claim
252 words
An integrated circuit memory system comprising: a read-only memory; a patch-memory on a substrate common to said read-only memory for patching predetermined blocks of said read-only memory; an input address bus connected to said read-only memory and said patch memory; a control logic unit comprising decoding circuitry for enabling a predetermined portion of said patch memory in response to a predetermined address on said address bus; and output means responsive to said predetermined address for connecting data from either said read-only memory or said patch memory to at least one input/output terminal, characterized in that: said memory system further comprises a nonvolatile random-access memory, sharing a common address space with said read-only memory, said random access memory and said read-only memory combining to fill said address space; each of said random-access memory and said patch-memory comprises an array of volatile memory cells; said random-access memory is controlled by memory overhead circuitry, having a write control pin, for reading data out from and writing data into that portion of said array of volatile memory cells within a random-access portion of said common address space; said patch-memory and said random-access memory are both connected to a voltage-maintenance circuit containing circuit means responsive to a power supply voltage and to at least one battery voltage for maintaining data in said patch-memory and said random-access memory when said power supply voltage is below a predetermined threshold, whereby data in said array of volatile memory cells is preserved during periods when said power supply voltage is low.
Claim 3
Dependent Claim
74 words
A memory system according to claim 1, further characterized in that said control logic unit includes circuit-enabling means responsive to a predetermined pattern of signals on said address bus for enabling selected portions of said control logic unit to open a path between said input/output terminal and at least one of said patch memory cells, whereby access to said patch memory cells may be controlled by said pattern of signals on said address bus.
Claim 4
Dependent Claim
83 words
A memory system according to claim 2, further characterized in that said predetermined pattern of signals comprises a pattern of signals representative of at least one predetermined address in said read-only memory and in that said memory overhead circuitry, including said write control pin, is controlled in a random-access write configuration to process a write operation to an address within said random-access memory, whereby said circuit-enabling means is responsive to the combination of an address within read-only memory and said random-access write configuration.
Claim 5
Independent Claim
159 words
A method of manipulating data in a portion of a patch-ROM memory array within an integrated circuit memory system having ROM, RAM and patch-ROM memory arrays, said ROM and RAM having a ROM address range and a RAM address range, respectively, that combine to fill a system memory range, whereby said patch-ROM memory array does not have predetermined addresses within said system memory range, said integrated circuit having connection pins for control voltages within said system memory range, comprising the steps of: setting predetermined control voltage states on system control pins and said states are not unique to said patch-ROM manipulation; placing a first predetermined address within said ROM address range on a set of address lines as part of a first write sequence under control of said control voltage states; and placing an entrance address within said ROM address range on said address lines as part of a second write sequence under control of said control voltage states.
Claim 6
Independent Claim
159 words
A method of manipulating data in a portion of a patch-ROM memory array within an integrated circuit memory system having ROM, RAM and patch-ROM memory arrays, said ROM and RAM having a ROM address range and a RAM address range, respectively, that combine to fill a system memory range, whereby said patch-ROM memory array does not have predetermined addresses within said system memory range, said integrated circuit having connection pins for control voltages within said system memory range, comprising the steps of: setting predetermined control voltage states on system control pins and said states are not unique to said patch-ROM manipulation; placing a first predetermined address within said ROM address range on a set of address lines as part of a first write sequence under control of said control voltage states; and placing an entrance address within said ROM address range on said address lines as part of a second write sequence under control of said control voltage states.
Claim 7
Dependent Claim
96 words
A method according to claim 4 in which: said entrance address is the address of a first cell in a block of at least two cells with in said ROM address range; and including the further steps of consecutively setting a data value to be written into said first cell followed by data values to be written into succeeding ones of said block of cells on a data line connected to said block of at least two cells in response to said non-unique configuration of control pins and said entrance address within said ROM address range.
Claim 8
Dependent Claim
22 words
A method according to claim 4, in which said entrance address initiates an automatic sequence of steps manipulating said patch-ROM memory array.
Claim 9
Dependent Claim
15 words
A method according to claim 6, in which said patch-ROM memory array is automatically cleared.
Claim 10
Independent Claim
164 words
A method of manipulating data in a portion of a patch-ROM memory array within an integrated circuit memory system having ROM, RAM and patch-ROM memory arrays, said ROM and RAM having a ROM address range and a RAM address range, respectively, that combine to fill a system memory range, whereby said patch-ROM memory array does not have predetermined addresses within said system memory range, in the operation of which system there is a standard RAM write sequence of operations for writing data into said RAM, said integrated circuit having control and address pins comprising the steps of: setting predetermined control voltage states on system control pins and said states are not unique to said patch-ROM manipulating; placing a first predetermined address within said ROM address range on a set of address pins as part of a first standard RAM write sequence; and placing an entrance address within said ROM address range on said address pins as part of a second standard RAM write sequence.
Claim 11
Independent Claim
164 words
A method of manipulating data in a portion of a patch-ROM memory array within an integrated circuit memory system having ROM, RAM and patch-ROM memory arrays, said ROM and RAM having a ROM address range and a RAM address range, respectively, that combine to fill a system memory range, whereby said patch-ROM memory array does not have predetermined addresses within said system memory range, in the operation of which system there is a standard RAM write sequence of operations for writing data into said RAM, said integrated circuit having control and address pins comprising the steps of: setting predetermined control voltage states on system control pins and said states are not unique to said patch-ROM manipulating; placing a first predetermined address within said ROM address range on a set of address pins as part of a first standard RAM write sequence; and placing an entrance address within said ROM address range on said address pins as part of a second standard RAM write sequence.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-09-01 | 1990-03-03 | 1990-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-09-01 | 1994-03-03 | 1994-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-09-01 | 1998-03-03 | 1998-09-02 | $7700.00 | Window Closed / Lapsed |