Switched memory module

Claim 2

Method of operating a memory array in which a plurality of memory circuit devices are arranged in a manner such that memory information is obtained by addressing bits of information from a selected number of the memory devices in the array in a format, the devices being addressed by using address enable signals to address each device, and the format of bits form a byte of memory data such that each byte includes bits from each memory device in the selected number of the circuit devices, and wherein the bits are addressed as rows and columns of information in a matrix on each memory device, characterized by: (a) arranging the memory devices into a plurality of columns of memory devices, and a plurality of rows of memory devices; (b) selectively enabling the addressing of the different rows of the memory devices by selectively providing said address enable signals to the respective rows of the devices, wherein each of a selected number of the memory devices in one row are addressed simultaneously as an address command response and a like number of memory devices in other rows are addressed at different times, the addressing of the different rows of the memory devices being accomplished in like sequences of rows and columns on a plurality of the devices; (c) addressing each row of the memory devices while not enabling the memory devices in the other rows to be addressed.

Claim 3

Method as described as in claim 1, further characterized by: (a) addressing each memory device by using addresses which are arranged in similar matrices of rows and columns on the memory device; and (b) using address commands for addressing of a row of memory devices to corresponding rows and columns on each memory device in a row of memory devices in response to said address commands.

Claim 4

Method as described in claim 2, further characterized by: using one of said memory devices in each row to provide parity information such that a column of the memory devices provides said parity information.

Claim 5

Method as described in claim 3, further characterized by: arranging the memory devices in four rows, wherein two bits of enable data are provided to each memory device, thereby causing selected rows of the memory devices to be enabled by said new bits of information.

Claim 6

Method as described in claim 2, further characterized by: using termination capacitors to compensate for a shifted impedance load of the memory devices caused by the multiple rows of said memory devices, when the multiple rows of said memory devices are provided with computer address signals at signal level intended for a single row of memory devices.

Claim 7

Method as described in claim 5, further characterized by: (a) arranging the memory devices in four rows;

Claim 8

(b) providing two bits of enable data to each memory device, thereby causing selected rows and of the memory devices to be enabled by said new bits of information.

Claim 9

(b) providing two bits of enable data to each memory device, thereby causing selected rows and of the memory devices to be enabled by said new bits of information.

Claim 10

Method as described in claim 6, further characterized by: (a) the memory devices being random access memory semiconductor devices, having read and write address bits thereon; (b) the two bits being row and column enable bits for the memory devices.

Claim 11

Method as described in claim 7, further characterized by: the memory devices being dynamic random access memories.

Claim 12

Method as described in claim 5, further characterized by: (a) using a computer to provide address signals to an address circuit; and (b) responding to address signals with the address circuit and addressing the memory devices in a sequence which permits said selective enablement.

Claim 13

Method as described in claim 9, further characterized by: (a) generating the address signals with a driver; and (b) providing the address signals to said address circuit in response to signals received from the computer.

Claim 14

Method as described in claim 9, further characterized by: (a) said address circuit being a programmable array logic circuit; and (b) controlling the enablement of memory devices in said memory array with the programable array logic device.

Claim 15

Method as described in claim 1, characterized by: arranging the array on a printed circuit board having an edge connector, wherein the edge connector is insertable into a data bus slot in lieu of a single row of said memory devices.

Claim 16

Method as described in claim 12, further characterized by: (a) arranging addresses on each memory device in similar matrices of rows and columns on the memory device; (b) the addressing of a row of memory devices being accomplished to corresponding rows and columns on each memory device in a row of memory devices in response to address commands; (c) responding to address signals received from a computer with an address circuit and addressing the memory devices in a sequence which permits said selective enablement; (d) providing address signals to said address circuit with a driver, in response to signals received from the computer; and (e) using termination capacitors to compensate for a shifted impedance load of the memory devices caused by the multiple rows of said memory devices, when the multiple rows of said memory devices are provided with computer address signals at signal levels intended for a single row of memory devices.

Claim 17

Method as described in claim 13, further characterized by: (a) said address circuit being a programmable array logic circuit; and (b) controlling the enablement of memory devices in said memory array with the programmable array logic device.

Claim 18

Method of operating a memory array in which a plurality of memory circuit devices are mounted on a printed circuit board which includes an edge connector for connection to a one-byte memory address bus and bits of information are addressed from a number of the memory devices in the array corresponding to a byte format, wherein the edge connector is insertable into a data bus slot in lieu of a single row of said memory devices, and wherein the bits are addressed as rows and columms of information in a matrix on each memory device, characterized by: (a) arranging the memory devices into a plurality of columns and a plurality of rows; (b) selectively enabling the addressing of the different rows of the memory devices, wherein each of a selected number of the memory devices in one row are addressed simultaneously as an address command response and a like number of memory devices on other rows are addressed at different times, the addressing of the different rows of the memory devices being accomplished in like sequences of columns; (c) addressing each row of the memory devices while not enabling the memory devices in the other rows to be addressed; (d) providing each memory device with addresses which are arranged in similar matrices of rows and columns on the memory device; (e) addressing of a row of memory devices to corresponding rows and columns on each memory device in a row of memory devices in response to address commands; (f) the memory devices being random access memory semiconductor devices, having read and write addess bits thereon; (g) providing two bits of enable data to each memory device, thereby causing selected rows and columns of the memory devices to be enabled by said new bits of information; (h) the two bits being row and column enable bits for the memory devices; (i) responding to address signals received from a computer and addressing the memory devices in a sequence which permits said selective enablement; and (j) providing address signals to said address circuit, in response to signals received from the computer.

Claim 19

Method of operating a memory array in which a plurality of memory circuit devices are mounted on a printed circuit board which includes an edge connector for connection to a one-byte memory address bus and bits of information are addressed from a number of the memory devices in the array corresponding to a byte format, wherein the edge connector is insertable into a data bus slot in lieu of a single row of said memory devices, and wherein the bits are addressed as rows and columms of information in a matrix on each memory device, characterized by: (a) arranging the memory devices into a plurality of columns and a plurality of rows; (b) selectively enabling the addressing of the different rows of the memory devices, wherein each of a selected number of the memory devices in one row are addressed simultaneously as an address command response and a like number of memory devices on other rows are addressed at different times, the addressing of the different rows of the memory devices being accomplished in like sequences of columns; (c) addressing each row of the memory devices while not enabling the memory devices in the other rows to be addressed; (d) providing each memory device with addresses which are arranged in similar matrices of rows and columns on the memory device; (e) addressing of a row of memory devices to corresponding rows and columns on each memory device in a row of memory devices in response to address commands; (f) the memory devices being random access memory semiconductor devices, having read and write addess bits thereon; (g) providing two bits of enable data to each memory device, thereby causing selected rows and columns of the memory devices to be enabled by said new bits of information; (h) the two bits being row and column enable bits for the memory devices; (i) responding to address signals received from a computer and addressing the memory devices in a sequence which permits said selective enablement; and (j) providing address signals to said address circuit, in response to signals received from the computer.

Claim 20

Method as described in claim 15, further characterized by: using termination capacitors to compensate for a shifted impedance load of the memory devices caused by the multiple rows of said memory devices, when provided with computer address signals at signal levels intended for a single row SIMM board.

Claim 21

Method as described in claim 16, further characterized by: the memory devices being arranged in four rows, wherein said two bits of enable data are provided to each memory device, thereby enabling selected rows and of the memory devices to be enabled by said new bits of information.

Claim 22

Method as described in claim 17, further characterized by: (a) said address circuit being a programmable array logic circuit; and (b) controlling the enablement of memory devices in said memory array with the programmable array logic device.

Claim 23

Method as described in claim 15, further characterized by: (a) using a computer to provide address signals to an address circuit; and (b) responding to address signals with the address circuit and addressing the memory devices in a sequence which permits said selective enablement.

Claim 24

Method as described in claim 19, further characterized by: (a) generating the address signals with a driver; and (b) providing the address signals to said address circuit in response to signals received from the computer.

Claim 25

Method as described in claim 19, further characterized by: (a) said address circuit being a programmable array logic circuit; and (b) controlling the enablement of memory devices in said memory array with the programmable array logic device.

Claim 26

Method as described in claim 19, characterized by: (a) arranging the array on a printed circuit board having an edge connector, wherein the edge connector is insertable into a data bus slot in lieu of a single row of said memory devices.