US3840864A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple memory unit controller
Assignee: Unisys Corp
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Filing: 1974-01-14
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Granted: 1974-10-08
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Expires: 1994-01-14
Abstract
Abstract A memory control unit for determining the actual physical location of an instruction address in one of a plurality of memory units in a digital computer wherein the instruction address and the memory addresses are both in a block, track and word hierarchy, where the instruction address may not correspond to the memory address due to differences in the number of available blocks for recording program instructions from memory unit to memory unit, utilizing: a block address register for storing the block portion of the instruction address; a shift register associated with each memory unit wherein the number of available blocks for each memory unit is stored; a flip flop for bit by bit comparison of the contents of the block address register with the contents of selected shift registers; a counter for shifting from one to another of the shift registers when the contents of the block register exceeds the contents of the selected shift register, and an adder for decrementing the contents of the block address register by an amount equal to the number contained in the previously selected shift register. The memory control unit also includes another flip flop responding to the bit by bit serial comparison of the block address register and the selected shift register for detecting whether the instruction address starts in the last available block in a memory unit, and a circuit for evaluating the track and word portion of the address of each word of the instruction being executed for determining when the last word of an instruction has been executed by the computer.
Inventors
- 👤 H Chang
- 👤 S Aggarwal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 03:13
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
217 words
In a digital computer having at least one memory unit, each said memory unit having a predetermined number of available blocks for storing instructions, wherein each location in the memory unit is identified by an address in a block, track, and word hierarchy and the instruction addresses in a program being similarly in a block, track, and word hierarchy, a memory control unit for determining the location of a desired instruction address in the memory unit comprising: a block address register for storing the block portion of the instruction address; a plurality of shift registers, wherein an individual shift register is associated with a said memory unit and contains information indicating the number of blocks in said associated memory unit which are available for use; comparison means for comparing the contents of said block address register with the contents of a selected one of said shift registers; decrementing means responsive to said comparing means for decrementing the contents of said block address register by the contents of said selected shift register when the contents of said block address register exceeds the contents of said selected shift register; and selecting means responsive to said comparing means for selecting another of said shift registers when the contents of said block register exceeds the contents of said selected shift register.
Claim 2
Dependent Claim
217 words
In a digital computer having at least one memory unit, each said memory unit having a predetermined number of available blocks for storing instructions, wherein each location in the memory unit is identified by an address in a block, track, and word hierarchy and the instruction addresses in a program being similarly in a block, track, and word hierarchy, a memory control unit for determining the location of a desired instruction address in the memory unit comprising: a block address register for storing the block portion of the instruction address; a plurality of shift registers, wherein an individual shift register is associated with a said memory unit and contains information indicating the number of blocks in said associated memory unit which are available for use; comparison means for comparing the contents of said block address register with the contents of a selected one of said shift registers; decrementing means responsive to said comparing means for decrementing the contents of said block address register by the contents of said selected shift register when the contents of said block address register exceeds the contents of said selected shift register; and selecting means responsive to said comparing means for selecting another of said shift registers when the contents of said block register exceeds the contents of said selected shift register.
Claim 3
Dependent Claim
39 words
The memory control unit of claim 1 wherein the contents of said block address register and said plurality of registers are in binary form and wherein said comparing means is a flip flop for bit by bit serial comparison.
Claim 4
Dependent Claim
19 words
The memory control unit of claim 1 additionally including means for complementing the contents of said selected shift register.
Claim 5
Dependent Claim
31 words
The memory control unit of claim 3 wherein said decrementing means includes a binary adder for combining the contents of said block address register with the output of said complementing means.
Claim 6
Dependent Claim
29 words
The memory control unit of claim 1 additionally including last block detection means for determining when the instruction address is addressing the last available block in a memory unit.
Claim 7
Dependent Claim
41 words
The memory control unit of claim 5 wherein the contents of said block address register and said selected shift register are in binary form and wherein said last block detection means is a flip flop for bit by bit serial comparison.
Claim 8
Dependent Claim
45 words
The memory control unit of claim 5 additionally including means responsive to said last block detection means for evaluating the track and word portions of the instruction being executed to thereby determine when the last instruction word in said last available block has been executed.
Claim 9
Dependent Claim
54 words
The memory control unit of claim 7 wherein the contents of said block address register and said selected shift register are in binary form and wherein said last block detecting means is a flip flop for bit by bit serial comparison of the contents of said block address register and said selected shift register.
Claim 10
Dependent Claim
219 words
A memory control unit for use in a digital computer having a plurality of memory units wherein each memory location is identified by an address in a block, track, and word hierarchy, and, wherein instruction addresses of program instructions are similarly formatted in a block, track and word hierarchy, said memory control unit being used for determining the location of the first word of an instruction in a said memory unit, comprising: a block address register for storing the block portion of a said instruction address; a plurality of shift registers, wherein each shift register is associated with a memory unit and contains information indicating the number of blocks in said associated memory unit which are available for use; a comParison flip flop responsive to the contents of said block address register and said selected shift register; a complementing circuit which complements the contents of said selected shift register; a binary adder responsive to the contents of said block address register and said complementing circuit for decrementing the contents of said block address register by the contents of said selected shift register; a select counter responsive to said comparison flip flop for selecting another of said shift registers; and a last block detection flip flop responsive to the contents of said block address register and said selected shift register.
Claim 11
Dependent Claim
219 words
A memory control unit for use in a digital computer having a plurality of memory units wherein each memory location is identified by an address in a block, track, and word hierarchy, and, wherein instruction addresses of program instructions are similarly formatted in a block, track and word hierarchy, said memory control unit being used for determining the location of the first word of an instruction in a said memory unit, comprising: a block address register for storing the block portion of a said instruction address; a plurality of shift registers, wherein each shift register is associated with a memory unit and contains information indicating the number of blocks in said associated memory unit which are available for use; a comParison flip flop responsive to the contents of said block address register and said selected shift register; a complementing circuit which complements the contents of said selected shift register; a binary adder responsive to the contents of said block address register and said complementing circuit for decrementing the contents of said block address register by the contents of said selected shift register; a select counter responsive to said comparison flip flop for selecting another of said shift registers; and a last block detection flip flop responsive to the contents of said block address register and said selected shift register.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-10-07 | 1978-04-08 | 1978-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-10-07 | 1982-04-08 | 1982-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-10-07 | 1986-04-08 | 1986-10-08 | $7700.00 | Window Closed / Lapsed |