Patent FR1578772A successfully refreshed from Google Patents.
Patent US5681772A successfully refreshed from Google Patents.
US5681772A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Through glass ROM code implant to reduce product delivering time
Assignee: Promos Technologies Inc
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Filing: 1996-05-30
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Granted: 1997-10-28
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Expires: 2016-05-30
Abstract
Abstract A read only memory semiconductor integrated circuit device includes an improved cell region and a method of manufacture therefor. The improved cell region includes a recessed dielectric region overlying a gate electrode region. Such recessed dielectric region allows for an implanting or coding step to occur after the dielectric layer is applied to the surface of the device. Coding of the ROM device during a latter processing step shortens product turn-around-time. The improved cell also includes an improved method of manufacture. Such method provides for a dielectric layer formed over a gate electrode of a partially completed device. The method further provides etching the upper portion of the dielectric layer overlying the gate electrode to form a recessed region. A step of coding or implanting is then performed to change the device from enhancement mode into depletion mode, thereby providing the ROM code for the designated cell.
Inventors
- 👤 Min-Liang Chen
- 👤 Ying-Kit Tsui
- 👤 Jau-Nan Kau
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:36
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
86 words
A method of forming a semiconductor device comprising the steps of: providing a partially completed semiconductor device comprising at least a gate electrode and a channel region; forming a dielectric layer overlying said gate electrode; removing a thickness of said dielectric layer overlying said gate electrode to form a dielectric layer comprising a recessed region, said dielectric layer having a remaining thickness overlying said gate electrode; implanting impurities through said remaining thickness and through at least a portion of said gate electrode; and annealing said implant.
Claim 2
Independent Claim
86 words
A method of forming a semiconductor device comprising the steps of: providing a partially completed semiconductor device comprising at least a gate electrode and a channel region; forming a dielectric layer overlying said gate electrode; removing a thickness of said dielectric layer overlying said gate electrode to form a dielectric layer comprising a recessed region, said dielectric layer having a remaining thickness overlying said gate electrode; implanting impurities through said remaining thickness and through at least a portion of said gate electrode; and annealing said implant.
Claim 3
Dependent Claim
19 words
The method of claim 1 wherein said impurities are impurities having an absolute charge greater than one electron volt.
Claim 4
Dependent Claim
17 words
The method of claim 2 wherein said implanting step is at an energy greater than 150 keV.
Claim 5
Dependent Claim
17 words
The method of claim 1 wherein said dielectric layer is a BPSG layer overlying an oxide layer.
Claim 6
Dependent Claim
19 words
The method of claim 1 wherein said partially completed semiconductor device is an MOS device for a ROM cell.
Claim 7
Dependent Claim
33 words
The method of claim 1 further comprising a step of forming a masking layer overlying said dielectric layer before said removing step, said masking layer having an exposed region over said gate electrode.
Claim 8
Dependent Claim
19 words
The method of claim 1 wherein said impurities are selected from a group consisting of boron, phosphorous, and arsenic.
Claim 9
Dependent Claim
14 words
The method of claim 1 wherein said removing step is an anisotropic etching step.
Claim 10
Dependent Claim
16 words
The method of claim 1 wherein said implanting step implants impurities completely through said gate electrode.
Claim 11
Independent Claim
105 words
A method of implanting impurities in an integrated circuit device comprising the steps of: providing a partially completed semiconductor device comprising at least a polysilicon layer overlying a silicon substrate; forming a dielectric layer overlying said polysilicon layer; removing a thickness of said dielectric layer overlying said polysilicon layer to form a dielectric layer comprising a recessed region, said dielectric layer having a remaining thickness overlying said gate electrode; implanting impurities each having an absolute charge greater than one electron volt through said recessed region and through a portion of said polysilicon layer; and annealing said implant to drive-in said impurities into said silicon substrate.
Claim 12
Independent Claim
105 words
A method of implanting impurities in an integrated circuit device comprising the steps of: providing a partially completed semiconductor device comprising at least a polysilicon layer overlying a silicon substrate; forming a dielectric layer overlying said polysilicon layer; removing a thickness of said dielectric layer overlying said polysilicon layer to form a dielectric layer comprising a recessed region, said dielectric layer having a remaining thickness overlying said gate electrode; implanting impurities each having an absolute charge greater than one electron volt through said recessed region and through a portion of said polysilicon layer; and annealing said implant to drive-in said impurities into said silicon substrate.
Claim 13
Dependent Claim
17 words
The method of claim 10 wherein said implanting step is at an energy greater than 150 keV.
Claim 14
Dependent Claim
17 words
The method of claim 10 wherein said dielectric layer is a BPSG layer overlying an oxide layer.
Claim 15
Dependent Claim
29 words
The method of claim 12 wherein said BPSG layer and oxide layer after said removing step have a combined thickness ranging from about 1,500 Å to about 2,500 Å.
Claim 16
Dependent Claim
19 words
The method of claim 10 wherein said partially completed semiconductor device is an MOS device for a ROM cell.
Claim 17
Dependent Claim
33 words
The method of claim 10 further comprising a step of forming a masking layer overlying said dielectric layer before said removing step, said masking layer having an exposed region over said polysilicon layer.
Claim 18
Dependent Claim
19 words
The method of claim 10 wherein said impurities are selected from a group consisting of boron, phosphorous, and arsenic.
Claim 19
Dependent Claim
14 words
The method of claim 10 wherein said removing step is an anisotropic etching step.
Claim 20
Dependent Claim
16 words
The method of claim 10 wherein said implanting step implants impurities completely through said polysilicon layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-27 | 2001-04-28 | 2001-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-27 | 2005-04-28 | 2005-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-27 | 2009-04-28 | 2009-10-28 | $7700.00 | Window Closed / Lapsed |