US5270237A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing mask ROMs by using a protection layer
Assignee: Samsung Electronics Co Ltd
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Filing: 1992-04-23
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Granted: 1993-12-14
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Expires: 2012-04-23
Abstract
Abstract A method for manufacturing mask ROMs is disclosed, wherein a semiconductor substrate of a first conductive type, on which a gate insulating layer, a poly-silicon layer, source and drain regions and a spacer are formed is stored after depositing the entire surface of the structure with a protection layer until the next steps such as programming, so that the poly-silicon gate and the source and drain regions of the structure can be prevented from being polluted with organisms or matriums, etc. by forming a protection layer before the storage, thereby improving the efficiency and reliability of mask ROMs, and the ROM data region can be checked during the etching of the protecting layer for distinguishing the defective chips simply and efficiently in a short manufacturing time.
Inventors
- 👤 Jae H. Sang
- 👤 Young J. Kwon
- 👤 Jun K. Bae
- 👤 Kun O. Ahn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:15
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383; Y; Y10; Y10S; Y10S438/00; Y10S438/976
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
175 words
A method for manufacturing mask ROMs comprising the steps of: forming a plurality of spaced apart structures each comprising a gate insulating layer and an overlying poly-silicon gate on a surface of a semiconductor substrate of a first conductivity type; forming first ion implanted regions by injecting impurity ions of a second conductivity type into portions of said substrate adjoining said structures; activating the ions of said first ion implanted regions by means of a thermal treatment so as to form source and drain regions adjoining each of said structures; then forming a continuous protection layer on said surface and directly onto the poly-silicon gates of said structures; patterning said protection layer so as to directly expose selected ones only of said poly-silicon gates; forming second ion implanted regions by injecting impurity ions of said first conductivity type into said substrate only through said selected and exposed poly-silicon gates; and forming a passivation layer on said surface after forming channel regions underlying said selected structures by activating said ions of said second ion implanted regions.
Claim 2
Independent Claim
175 words
A method for manufacturing mask ROMs comprising the steps of: forming a plurality of spaced apart structures each comprising a gate insulating layer and an overlying poly-silicon gate on a surface of a semiconductor substrate of a first conductivity type; forming first ion implanted regions by injecting impurity ions of a second conductivity type into portions of said substrate adjoining said structures; activating the ions of said first ion implanted regions by means of a thermal treatment so as to form source and drain regions adjoining each of said structures; then forming a continuous protection layer on said surface and directly onto the poly-silicon gates of said structures; patterning said protection layer so as to directly expose selected ones only of said poly-silicon gates; forming second ion implanted regions by injecting impurity ions of said first conductivity type into said substrate only through said selected and exposed poly-silicon gates; and forming a passivation layer on said surface after forming channel regions underlying said selected structures by activating said ions of said second ion implanted regions.
Claim 3
Dependent Claim
25 words
The method of claim 1, comprising, after forming said protection layer and prior to patterning said protection layer, storing said substrate in an inert atmosphere.
Claim 4
Dependent Claim
137 words
A process of manufacturing a programmed memory device comprising providing a programmable structure comprising a semiconductor substrate containing a plurality of spaced apart, field effect transistors each comprising source and drain regions formed at a surface of said substrate and separated by a channel region covered by a gate insulating layer covered by a gate electrode, then covering the entire said surface and said layers and gate electrodes thereon with a continuous protective layer with said protective layer directly contacting said gate electrodes, then storing said protective layered structure in an inert atmosphere, and, after said storage step, programming said structure by patterning said protective layer to directly expose the gate electrodes of selected ones only of said transistors, and further processing only said selected transistors by injecting ions into said substrate through said exposed gate electrodes.
Claim 5
Dependent Claim
137 words
A process of manufacturing a programmed memory device comprising providing a programmable structure comprising a semiconductor substrate containing a plurality of spaced apart, field effect transistors each comprising source and drain regions formed at a surface of said substrate and separated by a channel region covered by a gate insulating layer covered by a gate electrode, then covering the entire said surface and said layers and gate electrodes thereon with a continuous protective layer with said protective layer directly contacting said gate electrodes, then storing said protective layered structure in an inert atmosphere, and, after said storage step, programming said structure by patterning said protective layer to directly expose the gate electrodes of selected ones only of said transistors, and further processing only said selected transistors by injecting ions into said substrate through said exposed gate electrodes.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1996-12-13 | 1997-06-14 | 1997-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-13 | 2001-06-14 | 2001-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-13 | 2005-06-14 | 2005-12-14 | $7700.00 | Window Closed / Lapsed |