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US5680344A
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Circuit and method of operating a ferrolectric memory in a DRAM mode
Assignee: Micron Technology Inc
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Filing: 1995-09-11
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Granted: 1997-10-21
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Expires: 2015-09-11
Abstract
Abstract A static ferroelectric memory circuit is described which has an array of ferroelectric memory cells fabricated as single capacitors using a ferroelectric dielectric and arranged as a static random access memory (SRAM). Data can be stored in a non-volatile manner on the memory cells by controlling the voltage placed upon the plates of the cell. A method is described for operating the ferroelectric memory as a dynamic random access memory (DRAM). Test methods are described for testing the memory cells and identifying whether a defect is result of a ferroelectric material defect or a physical defect, such as a short, open or high leakage.
Inventors
- 👤 Mirmajid Seyyedy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 20:21
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/22
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
101 words
A method of testing a static memory device comprising an array of ferroelectric memory cells fabricated as capacitors, each ferroelectric memory cell comprising a first plate and a second plate, the first plate connected to a plate line, the method comprising the steps of: coupling the plate line to a ground potential; storing a positive non-remnant charge on the ferroelectric memory cells; reading the ferroelectric memory cells which had a positive non-remnant charge stored thereon after a first predetermined time; and identifying short circuit failures of ferroelectric memory cells which did not retain the non-remnant charge during the first predetermined time.
Claim 2
Independent Claim
101 words
A method of testing a static memory device comprising an array of ferroelectric memory cells fabricated as capacitors, each ferroelectric memory cell comprising a first plate and a second plate, the first plate connected to a plate line, the method comprising the steps of: coupling the plate line to a ground potential; storing a positive non-remnant charge on the ferroelectric memory cells; reading the ferroelectric memory cells which had a positive non-remnant charge stored thereon after a first predetermined time; and identifying short circuit failures of ferroelectric memory cells which did not retain the non-remnant charge during the first predetermined time.
Claim 3
Dependent Claim
61 words
The method of claim 1 further comprising the steps of: reading the ferroelectric memory cells which had a positive non-remnant charge stored thereon after a second predetermined time; and identifying ferroelectric memory cell current leakage failures of memory cells which retained the non-remnant charge during the first predetermined time, but did not retain the non-remnant charge during the second predetermined time.
Claim 4
Dependent Claim
31 words
The method of claim 1 wherein the step of reading the ferroelectric memory cells comprises the step of: comparing a charge stored on the ferroelectric memory cells with a reference charge.
Claim 5
Dependent Claim
24 words
The method of claim 3 where the reference charge is generated by the step of producing a positive reference voltage using a non-remnant capacitor.
Claim 6
Dependent Claim
58 words
The method of claim 3 where the reference charge is generated by the step of: charging a non-remnant capacitor circuit to a pre-determined voltage; and sharing the charge stored on the non-remnant capacitor circuit with a bit line, where a capacitance of the bit line is an order of magnitude greater than the capacitance of the non-remnant capacitor.
Claim 7
Independent Claim
227 words
A method of testing a ferroelectric memory device comprising a first pair of bit line sections coupled to a sense amplifier, a second pair of bit line sections coupled to the sense amplifier, a first reference circuit having a plurality of ferroelectric reference cells coupled to the first pair of bit line sections, and a second reference circuit having a plurality of ferroelectric reference cells coupled to the second pair of bit line sections, the method of testing comprising the steps of: selecting a ferroelectric memory cell associated with a bit line of the first pair of bit line sections, the ferroelectric memory cell comprising a first plate and a second plate, the first plate connected to a plate line; coupling the plate line to a ground potential; storing a positive non-remnant charge on the selected ferroelectric memory cell; reading the selected ferroelectric memory cell which had a positive non-remnant charge stored thereon after a first predetermined time; coupling the bit line of the first pair of bit line sections to a first sensing node of the sense amplifier; activating the second reference circuit to produce a reference voltage; and coupling the second reference circuit to a second sensing node of the sense amplifier; identifying a short circuit failure if the selected ferroelectric memory cell which did not retain the non-remnant charge during the first predetermined time.
Claim 8
Independent Claim
227 words
A method of testing a ferroelectric memory device comprising a first pair of bit line sections coupled to a sense amplifier, a second pair of bit line sections coupled to the sense amplifier, a first reference circuit having a plurality of ferroelectric reference cells coupled to the first pair of bit line sections, and a second reference circuit having a plurality of ferroelectric reference cells coupled to the second pair of bit line sections, the method of testing comprising the steps of: selecting a ferroelectric memory cell associated with a bit line of the first pair of bit line sections, the ferroelectric memory cell comprising a first plate and a second plate, the first plate connected to a plate line; coupling the plate line to a ground potential; storing a positive non-remnant charge on the selected ferroelectric memory cell; reading the selected ferroelectric memory cell which had a positive non-remnant charge stored thereon after a first predetermined time; coupling the bit line of the first pair of bit line sections to a first sensing node of the sense amplifier; activating the second reference circuit to produce a reference voltage; and coupling the second reference circuit to a second sensing node of the sense amplifier; identifying a short circuit failure if the selected ferroelectric memory cell which did not retain the non-remnant charge during the first predetermined time.
Claim 9
Dependent Claim
99 words
The method of claim 6 wherein the step of activating the second reference circuit to produce a reference voltage comprises the steps of: coupling a first ferroelectric reference cell to a first bit line of the second pair of bit line sections, the first ferroelectric reference cell storing a first logic state; coupling a second ferroelectric reference cell to a second bit line of the second pair of bit line sections, the second ferroelectric reference cell storing a second logic state; reading the first and second ferroelectric reference cells; and electrically coupling the first and second bit lines together.
Claim 10
Dependent Claim
33 words
The method of claim 7 further including the steps of: restoring the first ferroelectric reference cell to a first logic state; and restoring the second ferroelectric reference cell to a second logic state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-20 | 2001-04-21 | 2001-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-20 | 2005-04-21 | 2005-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-20 | 2009-04-21 | 2009-10-21 | $7700.00 | Window Closed / Lapsed |