US5679589A
Expired / Lapsed
US
⏱️ 0.0 years remaining
FET with gate spacer
Assignee: Nokia of America Corp
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Filing: 1992-04-03
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Granted: 1997-10-21
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Expires: 2012-04-03
Abstract
Abstract A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adjacent double or triple layered gate spacers. The spacers permit precise tailoring of lightly doped drain junction profiles having deep and shallow junction portions. In addition, a self-aligned silicide may be formed solely over the deep junction portion thus producing a reliable low contact resistance connection to source and drain.
Inventors
- 👤 Kuo-Hua Lee
- 👤 Chih-Yuan Lu
- 👤 Janmye Sung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:38
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D64/00; H10D64/01; H10D64/021
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
92 words
A method of semiconductor integrated circuit fabrication comprising: forming a gate stack over a substrate, said gate having a first overlying nitride layer; forming a first oxide layer upon said gate stack and selected portions of said substrate; depositing a second layer of nitride upon said first oxide layer; depositing a second oxide layer upon said second nitride layer; etching said second oxide layer to form a first spacer; etching said second nitride layer to form a second spacer underlying said first spacer; said first nitride layer remaining upon said gate stack.
Claim 2
Independent Claim
92 words
A method of semiconductor integrated circuit fabrication comprising: forming a gate stack over a substrate, said gate having a first overlying nitride layer; forming a first oxide layer upon said gate stack and selected portions of said substrate; depositing a second layer of nitride upon said first oxide layer; depositing a second oxide layer upon said second nitride layer; etching said second oxide layer to form a first spacer; etching said second nitride layer to form a second spacer underlying said first spacer; said first nitride layer remaining upon said gate stack.
Claim 3
Dependent Claim
54 words
The method of claim 1 further including the steps of forming at least two junctions in said substrate; depositing a conductive material upon said substrate and upon at least one gate stack, said gate stack having said first nitride layer upon it, said conductive material contacting both of said junctions; patterning said conductive material.
Claim 4
Dependent Claim
25 words
The method of claim 2 wherein said conductive material is chosen from the group consisting of polysilicon, aluminum, tungsten, titanium, tantalum, metal silicide, or molybdenum.
Claim 5
Dependent Claim
59 words
The method of claim 1 which said step of forming a gate stack includes: growing an oxide layer upon said substrate; depositing a polysilicon layer on said oxide layer; depositing a nitride layer upon said polysilicon layer; and etching said oxide layer, said polysilicon layer, and said nitride layer to form said gate stack having an overlying nitride layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-20 | 2001-04-21 | 2001-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-20 | 2005-04-21 | 2005-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-20 | 2009-04-21 | 2009-10-21 | $7700.00 | Window Closed / Lapsed |