Fabrication method for integrated circuit structures including field effect transistors of sub-micrometer gate length, and integrated circuit structure fabricated by this method

Claim 1

A method for fabricating a semiconductor integrated circuit structure including at least some field effect transistor devices having a sub-micrometer gate length, on the basis of a semiconductor substrate (10) having a surface isolation pattern (12) which isolates regions of said semiconductor within said substrate from one another and which regions are designated to contain devices, characterized by the following steps: forming a silicon dioxide layer (16) which is designated to be in part the gate dielectric upon the surface of said substrate having the surface isolation pattern therein; depositing a conductive layer (20) upon said silicon dioxide layer; depositing a first silicon nitride layer (22) on said conductive layer; depositing a polycrystalline silicon layer (24) upon said silicon nitride layer; depositing a second silicon nitride layer (26); etching said second silicon nitride layer and said polycrystalline silicon layer so as to provide portions of said polycrystalline silicon layer having substantial vertical sidewalls; portions of said polycrystalline silicon layer extend across certain of said regions designated to contain devices and onto the surrounding isolation pattern; thermally oxidizing the said sidewalls to form a silicon dioxide sidewall layer (30). thereon; etching the remaining portions of said polycrystalline silicon layer and second silicon nitride layer; removing the undesired portions of said silicon dioxide sidewall layer (30); using said silicon dioxide sidewall layer as a mask, etching said first silicon nitride layer (22) and said conductive layer (20) to form the gate electrodes of field effect transistor devices in said conductive layer having a length determined by the dimension of said silicon dioxide sidewall layer (30); ion implanting conductivity imparting impurities adjacent to said gate electrodes to form source/drain elements for said field effect devices in said regions designated to contain devices; and forming an insulator layer over said devices with openings therein through which electrical contacts to the various elements of said devices are provided.

Claim 2

A method for fabricating a semiconductor integrated circuit structure including at least some field effect transistor devices having a sub-micrometer gate length, on the basis of a semiconductor substrate (10) having a surface isolation pattern (12) which isolates regions of said semiconductor within said substrate from one another and which regions are designated to contain devices, characterized by the following steps: forming a silicon dioxide layer (16) which is designated to be in part the gate dielectric upon the surface of said substrate having the surface isolation pattern therein; depositing a conductive layer (20) upon said silicon dioxide layer; depositing a first silicon nitride layer (22) on said conductive layer; depositing a polycrystalline silicon layer (24) upon said silicon nitride layer; depositing a second silicon nitride layer (26); etching said second silicon nitride layer and said polycrystalline silicon layer so as to provide portions of said polycrystalline silicon layer having substantial vertical sidewalls; portions of said polycrystalline silicon layer extend across certain of said regions designated to contain devices and onto the surrounding isolation pattern; thermally oxidizing the said sidewalls to form a silicon dioxide sidewall layer (30). thereon; etching the remaining portions of said polycrystalline silicon layer and second silicon nitride layer; removing the undesired portions of said silicon dioxide sidewall layer (30); using said silicon dioxide sidewall layer as a mask, etching said first silicon nitride layer (22) and said conductive layer (20) to form the gate electrodes of field effect transistor devices in said conductive layer having a length determined by the dimension of said silicon dioxide sidewall layer (30); ion implanting conductivity imparting impurities adjacent to said gate electrodes to form source/drain elements for said field effect devices in said regions designated to contain devices; and forming an insulator layer over said devices with openings therein through which electrical contacts to the various elements of said devices are provided.