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US5677865A
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Ferroelectric memory using reference charge circuit
Assignee: Micron Technology Inc
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Filing: 1995-09-11
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Granted: 1997-10-14
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Expires: 2015-09-11
Abstract
Abstract A random access memory circuit is described which uses single ferroelectric memory cells to store data. The ferroelectric memory cells can be selectively read using a reference voltage which is compared to a voltage representative of data stored on the memory cell using a multiplexed sense amplifier. The reference voltage is generated using a non-remnant capacitor circuit coupled to a bit line. In using a non-remnant capacitor circuit, a single-ended reference voltage can be generated on the bit line. The capacitance of the bit line is substantially greater than the capacitance of the non-remnant capacitor, therefore, the resultant reference voltage on the bit line remains relatively constant with fluctuations in supply voltage. A ferroelectric memory cell can then be read by comparing the voltage on its corresponding bit line to the reference voltage using the sense amplifier.
Inventors
- 👤 Mirmajid Seyyedy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:34
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/22
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
94 words
An integrated circuit memory comprising: an array of ferroelectric memory cells; a sense amplifier to sense and amplify data stored on the ferroelectric memory cells; first and second bit lines for coupling the ferroelectric memory cells to the sense amplifier; and reference circuitry selectively coupled to either the first or second bit line, the reference circuitry having a non-remnant capacitor circuit for providing a reference voltage, the non-remnant capacitor circuit is comprised of a conductor line having a line capacitance, and a plurality of capacitors selectively coupled to the conductor line via access devices.
Claim 2
Dependent Claim
94 words
An integrated circuit memory comprising: an array of ferroelectric memory cells; a sense amplifier to sense and amplify data stored on the ferroelectric memory cells; first and second bit lines for coupling the ferroelectric memory cells to the sense amplifier; and reference circuitry selectively coupled to either the first or second bit line, the reference circuitry having a non-remnant capacitor circuit for providing a reference voltage, the non-remnant capacitor circuit is comprised of a conductor line having a line capacitance, and a plurality of capacitors selectively coupled to the conductor line via access devices.
Claim 3
Independent Claim
61 words
A method of generating a reference voltage in a ferroelectric memory circuit, the method comprising the steps of: charging a non-remnant capacitor circuit to a pre-determined voltage; and sharing the charge stored on the non-remnant capacitor circuit with a bit line, where a capacitance of the bit line is an order of magnitude greater than the capacitance of the non-remnant capacitor.
Claim 4
Independent Claim
61 words
A method of generating a reference voltage in a ferroelectric memory circuit, the method comprising the steps of: charging a non-remnant capacitor circuit to a pre-determined voltage; and sharing the charge stored on the non-remnant capacitor circuit with a bit line, where a capacitance of the bit line is an order of magnitude greater than the capacitance of the non-remnant capacitor.
Claim 5
Independent Claim
116 words
A method of testing a cell margin in a ferroelectric memory comprising a plurality of ferroelectric memory cells, and a sense amplifier, the method comprising the steps of: (a) selectively coupling one of the ferroelectric memory cells to the sense amplifier, the one of the ferroelectric memory cells storing data represented by a high voltage; (b) producing a reference voltage using a non-remnant capacitor; (c) electrically coupling the reference voltage to the sense amplifier; (d) reading the data stored in the one of the ferroelectric memory cells using the sense amplifier; and (e) adjusting the reference voltage and repeating steps (a)-(d) until the data stored in the one of the ferroelectric memory cells is read erroneous.
Claim 6
Independent Claim
116 words
A method of testing a cell margin in a ferroelectric memory comprising a plurality of ferroelectric memory cells, and a sense amplifier, the method comprising the steps of: (a) selectively coupling one of the ferroelectric memory cells to the sense amplifier, the one of the ferroelectric memory cells storing data represented by a high voltage; (b) producing a reference voltage using a non-remnant capacitor; (c) electrically coupling the reference voltage to the sense amplifier; (d) reading the data stored in the one of the ferroelectric memory cells using the sense amplifier; and (e) adjusting the reference voltage and repeating steps (a)-(d) until the data stored in the one of the ferroelectric memory cells is read erroneous.
Claim 7
Dependent Claim
120 words
An integrated circuit memory comprising: a sense amplifier having first and second sensing nodes; a first pair of bit lines connected to the first and second sensing nodes of the sense amplifier; a second pair of bit lines connected to the first and second sensing nodes of the sense amplifier; ferroelectric memory cells coupled to the first and second pair of bit lines; a reference line having a capacitance; a plurality of capacitors coupled to the reference line through access transistors; and isolation devices connected to the reference line and the second pair of bit lines for coupling the reference line to either the first or second reference node of the sense amplifier via the second pair of bit lines.
Claim 8
Dependent Claim
120 words
An integrated circuit memory comprising: a sense amplifier having first and second sensing nodes; a first pair of bit lines connected to the first and second sensing nodes of the sense amplifier; a second pair of bit lines connected to the first and second sensing nodes of the sense amplifier; ferroelectric memory cells coupled to the first and second pair of bit lines; a reference line having a capacitance; a plurality of capacitors coupled to the reference line through access transistors; and isolation devices connected to the reference line and the second pair of bit lines for coupling the reference line to either the first or second reference node of the sense amplifier via the second pair of bit lines.
Claim 9
Dependent Claim
40 words
The integrated circuit memory of claim 4 wherein a capacitance of a bit line of the second bit line pair is an order of magnitude greater than a sum capacitance of the reference bit line and the plurality of capacitors.
Claim 10
Dependent Claim
28 words
The integrated circuit memory of claim 4 further comprising an electronic key for activating the access transistors to selectively couple the plurality of capacitors to the reference line.
Claim 11
Independent Claim
140 words
A method of reading a ferroelectric memory comprising a plurality of ferroelectric memory cells, first and second bit lines, and a sense amplifier, the method comprising the steps of: equilibrating the first and second bit lines to a ground potential; charging a non-remnant capacitor to a pre-determined positive voltage simultaneously with the equilibrating step; selectively coupling one of the ferroelectric memory cells to the sense amplifier via the first bit line; raising a voltage of a plate line of the one of the ferroelectric memory cells to extract data stored in the ferroelectric memory cells; sharing the charge stored on the non-remnant capacitor with the second bit line, where a capacitance of the second bit line is greater than the capacitance of the non-remnant capacitor; and electrically coupling the reference voltage to the sense amplifier via the second bit line.
Claim 12
Independent Claim
140 words
A method of reading a ferroelectric memory comprising a plurality of ferroelectric memory cells, first and second bit lines, and a sense amplifier, the method comprising the steps of: equilibrating the first and second bit lines to a ground potential; charging a non-remnant capacitor to a pre-determined positive voltage simultaneously with the equilibrating step; selectively coupling one of the ferroelectric memory cells to the sense amplifier via the first bit line; raising a voltage of a plate line of the one of the ferroelectric memory cells to extract data stored in the ferroelectric memory cells; sharing the charge stored on the non-remnant capacitor with the second bit line, where a capacitance of the second bit line is greater than the capacitance of the non-remnant capacitor; and electrically coupling the reference voltage to the sense amplifier via the second bit line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-13 | 2001-04-14 | 2001-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-13 | 2005-04-14 | 2005-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-13 | 2009-04-14 | 2009-10-14 | $7700.00 | Window Closed / Lapsed |