Logic synthesis method and logic synthesis apparatus

Claim 1

A logic synthesis method for synthesizing a gate level logic circuit using a computer based on behavioral description of LSI, comprising steps of: an input processing for inputting the behavioral description of said LSI and element information including at least an element area, a delay time of signal propagation and a power consumption; a logic synthesis processing for synthesizing a logic circuit taking area specification and speed specification into consideration based on said behavioral description and element information entered in said input processing; a high power consumption path retrieval processing, in a plurality of signal propagation paths in the logic circuit synthesized by said logic synthesis processing, obtaining respective power consumptions of logic elements existing on each of the signal propagation paths, which are respectively calculated based on counting the number of times of change in output of the logic elements, to obtain respective sums of the power consumptions of all the logic elements existing on the respective signal propagation paths and finding out a specific signal propagation path having a larger power consumption than another of said signal propagation paths; a level number reduction processing for reducing a number of level of a partial logic circuit constituting a part of said specific signal propagation path having a large power consumption which is found out by said high power consumption path retrieval processing, and producing another partial logic circuit a number of level of which is smaller than that of said partial logic circuit; and a circuit replacement processing for replacing said partial logic circuit constituting a part of said specific signal propagation path having a large power consumption by said another partial logic circuit created by said level number reduction processing.