Logic circuit generator

Claim 2

A logic circuit generator for automatically generating a logic circuit from a given functional description, comprising: logic synthesizing means for synthesizing a logic circuit that implements functions specified by said functional description; logic-level test vector generating a test vector for use in a fault detection by analyzing the logic circuit synthesized by said logic synthesizing means, and further for outputting a fault detection rate and results of a testability analysis regarding the generated test vector; judging means for deciding whether or not said fault detection rate outputted from said logic-level test vector generating means is greater than a predefined value; and circuit converting means for, when it is judged as a result of a decision made by said judging means that said fault detection rate is lower than the predefined value logic circuit synthesized by said logic synthesizing means according to said results of the testability analysis outputted from said logic-level test vector generating means so as to eliminate difficult-to-test portions of said logic circuit and redundancies thereof, and to satisfy given design restrictions, wherein said circuit converting means performs the following functions: (i) inserting a test circuit into a portion of said logic circuit according to said results of the testability analysis outputted from said logic-level test vector generating means; (ii) optimizing said logic circuit by eliminating redundancy in said logic circuit as a result of said test circuit insertion; and (iii) adjusting said logic circuit by converting said logic circuit obtained from said optimizing step so as to satisfy said given design restrictions when it is determined that said logic circuit obtained from said optimizing step does not satisfy said given design restrictions.

Claim 3

A logic circuit generator for automatically generating a logic circuit from a given functional description, comprising: logic synthesizing means for synthesizing a logic circuit that implements functions specified by said functional description; function-level test vector generating means for generating a test vector for use in a fault detection from said functional description; fault simulating means for performing a fault simulation to the logic circuit synthesized by said logic synthesizing means, using the test vector generated by said function-level test vector generating means, and for outputting a fault detection rate and results of a testability analysis regarding said generated test vector; judging means for deciding whether or not said fault detection rate outputted from said fault simulating means is greater than a predefined value; and circuit converting means for, when it is judged as a result of a decision made by said judging means that the fault detection rate is lower than the predefined value, converting logic circuit synthesized by said logic synthesizing means according to said results of the testability analysis outputted from said fault simulating means so as to eliminate difficult-to-test portions of said logic circuit and redundancies thereof, and to satisfy given design restrictions, wherein said circuit converting means performs the following functions: (i) inserting a test circuit into a portion of said logic circuit according to said results of the testability analysis outputted from said fault simulating means; (ii) optimizing said logic circuit by eliminating redundancy in said logic circuit as a result of said test circuit insertion; and (iii) adjusting said logic circuit by converting said logic circuit obtained from said optimizing step so as to satisfy said given design restrictions when it is determined that said logic circuit obtained from said optimizing step does not satisfy said given design restrictions.

Claim 4

A logic circuit generator for automatically generating a logic circuit from a given functional description, comprising: logic synthesizing means for synthesizing a logic circuit that implements functions specified by said functional description; function-level test vector generating means for generating a test vector for use in a fault detection from said functional description; fault simulating means for performing a fault simulation to the logic circuit synthesized by said logic synthesizing means, using the test vector generated by said function-level test vector generating means, and for outputting a fault detection rate and results of a testability analysis regarding said generated test vector; judging means for deciding whether or not said fault detection rate outputted from said fault simulating means is greater than a predefined value; and circuit converting means for, when it is judged as a result of a decision made by said judging means that the fault detection rate is lower than the predefined value, converting logic circuit synthesized by said logic synthesizing means according to said results of the testability analysis outputted from said fault simulating means so as to eliminate difficult-to-test portions of said logic circuit and redundancies thereof, and to satisfy given design restrictions, wherein said circuit converting means performs the following functions: (i) inserting a test circuit into a portion of said logic circuit according to said results of the testability analysis outputted from said fault simulating means; (ii) optimizing said logic circuit by eliminating redundancy in said logic circuit as a result of said test circuit insertion; and (iii) adjusting said logic circuit by converting said logic circuit obtained from said optimizing step so as to satisfy said given design restrictions when it is determined that said logic circuit obtained from said optimizing step does not satisfy said given design restrictions.

Claim 5

A logic circuit generator for automatically generating a logic circuit from a given functional description, comprising: logic synthesizing means for synthesizing a logic circuit that implements functions specified by said given functional description; function-level test vector generating means for generating a first test vector from said given functional description; fault simulating means for performing a fault simulation to the logic circuit synthesized by said logic synthesizing means, using said first test vector generated by said function-level test vector generating means, and for outputting a first fault detection rate and a first list of undetected faults regarding said first test vector; judging means for deciding whether or not said first fault detection rate is higher than a predefined value; logic-level test vector generating means for generating a second test vector by analyzing said logic circuit according to said first list of undetected faults, and further for outputting a second fault detection rate and results of a testability analysis obtained when the generated second test vector and said first test vector are combined together, said second fault detection rate being inputted to said judging means; and circuit converting means for, when it is judged as a result of a decision made by said judging means that said second fault detection rate is lower than the predefined value, converting said logic circuit synthesized by said logic-level synthesizing means according to said results of the testability analysis outputted from said logic-level test vector generating means so as to eliminate difficult-to-test portions of said logic circuit and redundancies thereof, and to satisfy given design restrictions, wherein said circuit converting means performs the following functions: (i) inserting a test circuit into a portion of said logic circuit according to said results of the testability analysis outputted from said logic-level test vector generating means; (ii) optimizing said logic circuit by eliminating redundancy in said logic circuit as a result of said test circuit insertion; and (iii) adjusting said logic circuit by converting said logic circuit obtained from said optimizing step so as to satisfy said given design restrictions when it is determined that said logic circuit obtained from said optimizing step does not satisfy said given design restrictions.

Claim 6

A logic circuit generator for automatically generating a logic circuit from a given functional description, comprising: logic synthesizing means for synthesizing a logic circuit that implements functions specified by said given functional description; function-level test vector generating means for generating a first test vector from said given functional description; fault simulating means for performing a fault simulation to the logic circuit synthesized by said logic synthesizing means, using said first test vector generated by said function-level test vector generating means, and for outputting a first fault detection rate and a first list of undetected faults regarding said first test vector; judging means for deciding whether or not said first fault detection rate is higher than a predefined value; logic-level test vector generating means for generating a second test vector by analyzing said logic circuit according to said first list of undetected faults, and further for outputting a second fault detection rate and results of a testability analysis obtained when the generated second test vector and said first test vector are combined together, said second fault detection rate being inputted to said judging means; and circuit converting means for, when it is judged as a result of a decision made by said judging means that said second fault detection rate is lower than the predefined value, converting said logic circuit synthesized by said logic-level synthesizing means according to said results of the testability analysis outputted from said logic-level test vector generating means so as to eliminate difficult-to-test portions of said logic circuit and redundancies thereof, and to satisfy given design restrictions, wherein said circuit converting means performs the following functions: (i) inserting a test circuit into a portion of said logic circuit according to said results of the testability analysis outputted from said logic-level test vector generating means; (ii) optimizing said logic circuit by eliminating redundancy in said logic circuit as a result of said test circuit insertion; and (iii) adjusting said logic circuit by converting said logic circuit obtained from said optimizing step so as to satisfy said given design restrictions when it is determined that said logic circuit obtained from said optimizing step does not satisfy said given design restrictions.

Claim 7

A logic circuit generating method for automatically generating a logic circuit from a given functional description, comprising the steps of synthesizing a logic circuit which satisfies functions defined according to said given functional description; generating a test vector in a logic level for testing said logic circuit synthesized by analyzing said logic circuit and outputting a fault detection rate and additionally outputting results of a testability analysis regarding said test vector generated, said fault detection rate being defined as a ratio of detected faults to all faults; judging whether or not said fault detection rate is higher than a predefined value; and, when said fault detection rate is judged to be lower than the predefined value, deforming said logic circuit according to said results of the testability analysis so as to eliminate difficult-to-test portions of said logic circuit and redundancies thereof, and to satisfy given design restrictions, wherein said deforming step comprises: (i) inserting a test circuit into a portion of said logic circuit according to said results of the testability analysis; (ii) optimizing said logic circuit by eliminating redundancy in said logic circuit as a result of said test circuit insertion; and (iii) adjusting said logic circuit by converting said logic circuit obtained from said optimizing step so as to satisfy said given design restrictions when it is determined that said logic circuit obtained from said optimizing step does not satisfy said given design restrictions.

Claim 8

A logic circuit generating method for automatically generating a logic circuit from a given functional description, comprising the steps of synthesizing a logic circuit which satisfies functions defined according to said given functional description; generating a test vector in a logic level for testing said logic circuit synthesized by analyzing said logic circuit and outputting a fault detection rate and additionally outputting results of a testability analysis regarding said test vector generated, said fault detection rate being defined as a ratio of detected faults to all faults; judging whether or not said fault detection rate is higher than a predefined value; and, when said fault detection rate is judged to be lower than the predefined value, deforming said logic circuit according to said results of the testability analysis so as to eliminate difficult-to-test portions of said logic circuit and redundancies thereof, and to satisfy given design restrictions, wherein said deforming step comprises: (i) inserting a test circuit into a portion of said logic circuit according to said results of the testability analysis; (ii) optimizing said logic circuit by eliminating redundancy in said logic circuit as a result of said test circuit insertion; and (iii) adjusting said logic circuit by converting said logic circuit obtained from said optimizing step so as to satisfy said given design restrictions when it is determined that said logic circuit obtained from said optimizing step does not satisfy said given design restrictions.

Claim 9

A logic circuit generating method for automatically generating a logic circuit from a given functional description, comprising the steps of: synthesizing a logic circuit which satisfies functions defined according to said given functional description; generating test vectors in a functional level for testing said logic circuit according to said given functional description; performing a fault simulation about said logic circuit synthesized using said test vectors generated, and outputting a fault detection rate of said test vector and results obtained by analyzing testability of said logic circuit; judging whether or not said fault detection rate is higher than a predefined value; and converting said logic circuit synthesized based on said results obtained by the testability analysis, when said fault detection rate is judged to be lower than the predefined value, so as to eliminate difficult-to-test portions of said logic circuit and redundancies thereof and to satisfy given design restrictions, wherein said converting step comprises: (i) inserting a test circuit into a portion of said logic circuit according to said results of the testability analysis; (ii) optimizing said logic circuit by eliminating redundancy in said logic circuit as a result of said test circuit insertion; and (iii) adjusting said logic circuit by converting said logic circuit obtained from said optimizing step so as to satisfy said given design restrictions when it is determined that said logic circuit obtained from said optimizing step does not satisfy said given design restrictions.

Claim 10

A logic circuit generating method for automatically generating a logic circuit from a given functional description, comprising the steps of: synthesizing a logic circuit which satisfies functions defined according to said given functional description; generating test vectors in a functional level for testing said logic circuit according to said given functional description; performing a fault simulation about said logic circuit synthesized using said test vectors generated, and outputting a fault detection rate of said test vector and results obtained by analyzing testability of said logic circuit; judging whether or not said fault detection rate is higher than a predefined value; and converting said logic circuit synthesized based on said results obtained by the testability analysis, when said fault detection rate is judged to be lower than the predefined value, so as to eliminate difficult-to-test portions of said logic circuit and redundancies thereof and to satisfy given design restrictions, wherein said converting step comprises: (i) inserting a test circuit into a portion of said logic circuit according to said results of the testability analysis; (ii) optimizing said logic circuit by eliminating redundancy in said logic circuit as a result of said test circuit insertion; and (iii) adjusting said logic circuit by converting said logic circuit obtained from said optimizing step so as to satisfy said given design restrictions when it is determined that said logic circuit obtained from said optimizing step does not satisfy said given design restrictions.

Claim 11

A logic circuit generating method for automatically generating a logic circuit from a given functional description, comprising the steps of: synthesizing a logic circuit which satisfies functions defined according to said given functional description; generating a first test vector in a functional level according to said given functional description; executing a fault simulation with respect to said logic circuit synthesized, using said first test vector to evaluate a first fault detection rate when said first test vector is used, and to output a first list of undetected faults; judging whether or not said first fault detection rate is higher than a predefined value; generating a second test vector by analyzing said first list of undetected faults, and outputting a second fault detection rate and results of a testability analysis obtained from a combined vector of said first and second test vectors; and deforming, when said second fault detection rate is judged to be lower than the predefined value, said logic circuit based on said results of said testability analysis so as to eliminate difficult-to-test portions of said logic circuit and redundancies thereof, and to satisfy given design restrictions, wherein said deforming step comprises: (i) inserting a test circuit into a portion of said logic circuit according to said results of the testability analysis; (ii) optimizing said logic circuit by eliminating redundancy in said logic circuit as a result of said test circuit insertion; and (iii) adjusting said logic circuit by converting said logic circuit obtained from said optimizing step so as to satisfy said given design restrictions when it is determined that said logic circuit obtained from said optimizing step does not satisfy said given design restrictions.

Claim 12

A logic circuit generating method for automatically generating a logic circuit from a given functional description, comprising the steps of: synthesizing a logic circuit which satisfies functions defined according to said given functional description; generating a first test vector in a functional level according to said given functional description; executing a fault simulation with respect to said logic circuit synthesized, using said first test vector to evaluate a first fault detection rate when said first test vector is used, and to output a first list of undetected faults; judging whether or not said first fault detection rate is higher than a predefined value; generating a second test vector by analyzing said first list of undetected faults, and outputting a second fault detection rate and results of a testability analysis obtained from a combined vector of said first and second test vectors; and deforming, when said second fault detection rate is judged to be lower than the predefined value, said logic circuit based on said results of said testability analysis so as to eliminate difficult-to-test portions of said logic circuit and redundancies thereof, and to satisfy given design restrictions, wherein said deforming step comprises: (i) inserting a test circuit into a portion of said logic circuit according to said results of the testability analysis; (ii) optimizing said logic circuit by eliminating redundancy in said logic circuit as a result of said test circuit insertion; and (iii) adjusting said logic circuit by converting said logic circuit obtained from said optimizing step so as to satisfy said given design restrictions when it is determined that said logic circuit obtained from said optimizing step does not satisfy said given design restrictions.