US5111459A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electronic circuit tester
Assignee: DRAXY (SARL) RUE DU RIF IRONCHARD - LE FONTANIL CORNILLON
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Filing: 1987-09-17
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Granted: 1992-05-05
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Expires: 2007-09-17
Abstract
Abstract An electronic circuit tester according to the invention comprises: a connection board for connection with each of the terminals of the circuit to be tested; n boards (16), called electronic pins, comprising signal shaping means each of which is connected to an input of the connection board; a single test vector memory unit (17) containing all the test vectors for the circuit and from the circuit, those vectors transiting through said electronic pins; a central processing unit (10) for managing the system and the external links; in which the management of the vector memory is made alternatively by a memory management unit (22 ) connected independently from the other tester units to the central processing unit (10) or by an address processor (23) asynchronously operating with respect to the central processing unit.
Inventors
- 👤 Yves DeVigne
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:28
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31919; G01R31/31926
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
139 words
Electronic circuit tester comprising: a connection board (24) for connection with each of the terminals of a circuit to be tested; n boards (16), called electronic pins, comprising signal shaping means each of which is connected to an input of the connection board; a single test vector memory means for (17) containing all the test vectors for the circuit and from the circuit, including means for controlling application of said test vectors to the circuit to be tested through said electronic pins; a central process unit (10) for managing the tester and external links; wherein the management of the vector memory is made by at least one of a memory management unit (22) connected independently from other tester units to the central processing unit (10) and an address processor (23) operating asynchronously with respect to the central processing unit.
Claim 2
Dependent Claim
139 words
Electronic circuit tester comprising: a connection board (24) for connection with each of the terminals of a circuit to be tested; n boards (16), called electronic pins, comprising signal shaping means each of which is connected to an input of the connection board; a single test vector memory means for (17) containing all the test vectors for the circuit and from the circuit, including means for controlling application of said test vectors to the circuit to be tested through said electronic pins; a central process unit (10) for managing the tester and external links; wherein the management of the vector memory is made by at least one of a memory management unit (22) connected independently from other tester units to the central processing unit (10) and an address processor (23) operating asynchronously with respect to the central processing unit.
Claim 3
Dependent Claim
74 words
A tester according to claim 1, wherein each electronic pin comprises, on the same board, wave-form generating means (30) and amplitude shaping means, said wave-form generating means being programmable by digital signals from the CPU, said amplitude shaping means being programmable by analog signals, the tester further comprising an analog level generating circuit (19) external to the electronic pins, converting digital signals from the CPU to analog signals provided to all the electronic pins.
Claim 4
Dependent Claim
40 words
A tester according to claim 2, wherein said wave-form generating means comprise: a programmable latch circuit (30, 41-43) for timing providing a suitable delay to the test vectors transmitted by said electronic pin, and a circuit (19') providing said delay.
Claim 5
Dependent Claim
59 words
A tester according to claim 1, further comprising an analog central measuring unit (18), wherein each electronic pin (16) further comprises on the same board a multiplexing circuit (36) for connecting the circuit to be tested at least one of to said vector memory through the circuits of the electronic pin and to the analog central measuring unit (18).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-05 | 1995-11-04 | 1996-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-05 | 1999-11-04 | 2000-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-05 | 2003-11-04 | 2004-05-05 | $7700.00 | Window Closed / Lapsed |