Patent US771413A successfully refreshed from Google Patents.
Patent US5672533A successfully refreshed from Google Patents.
US5672533A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Field effect transistor having impurity regions of different depths and manufacturing method thereof
Assignee: Mitsubishi Electric Corp
•
Filing: 1995-11-09
•
Granted: 1997-09-30
•
Expires: 2015-11-09
Abstract
Abstract Disclosed is a semiconductor memory device in which defects in crystal in a junction region between a capacitor and a source/drain region, and a short channel effect of a transistor can be effectively reduced. The semiconductor memory device includes, on the side of a gate electrode at which the capacitor is connected, a sidewall formed to have a width larger than that of a sidewall on the side of a bit line, and a source/drain region to which the capacitor is connected and which is formed to have a diffusion depth larger than that of the opposite source/drain region. Therefore, the source/drain region effectively prevents defects in crystal from being produced in the junction region between the capacitor and the source/drain region connected to the capacitor and the sidewall effectively reduces the short channel effect.
Inventors
- 👤 Hideaki Arima
- 👤 Makoto Ohi
- 👤 Natsuo Ajika
- 👤 Atsushi Hachisuka
- 👤 Tomonori Okudaira
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 14:32
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10D30/603; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/09; H10B12/30; H10B12/48; H10B12/488; H10D30/01; H10D30/021; H10D30/0221
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
373 words
A method of manufacturing a semiconductor device including a memory cell array region and a peripheral circuit region, each of said memory cell array region and said peripheral circuit region having a field effect transistor, comprising the steps of: forming a first gate electrode on a semiconductor substrate in said memory cell array region, and a second gate electrode on the semiconductor substrate in said peripheral circuit region; forming a first sidewall insulation film on sidewalls of said first gate electrode in said memory cell array region and a second sidewall insulation film on sidewalls of said second gate electrode in said peripheral circuit region; forming a first impurity region in the memory cell array region and a second impurity region in the peripheral circuit region by implanting impurity ions with said first and second sidewall insulation films as a mask; forming a conductive layer and a first insulation film on said first impurity region and said first sidewall insulation film in said memory cell array region, and on said second impurity region and said second sidewall insulation film in said peripheral circuit region, and patterning said conductive layer and said first insulation film into a configuration to form a first insulator layer on a first conductor layer in said memory cell array region and a second insulator layer on a second conductor layer in said peripheral circuit region; forming a second insulation film all over said semiconductor substrate and anisotropically etching the second insulation film to form a third sidewall insulation film on a sidewall of said first conductor layer and on a portion of said first sidewall insulation film formed on sidewalls of said first gate electrode in said memory cell array region, and a fourth sidewall insulation film on a sidewall of said second conductor layer and on a portion of said second sidewall insulation film formed on sidewalls of said second gate electrode in said peripheral circuit region; and forming a third impurity region in said memory cell array region and a fourth impurity region in said peripheral circuit region by diffusing the impurities introduced in a third conductive layer, formed on said third sidewall insulation film and on the semiconductor substrate, into said semiconductor substrate by heat treatment.
Claim 2
Independent Claim
373 words
A method of manufacturing a semiconductor device including a memory cell array region and a peripheral circuit region, each of said memory cell array region and said peripheral circuit region having a field effect transistor, comprising the steps of: forming a first gate electrode on a semiconductor substrate in said memory cell array region, and a second gate electrode on the semiconductor substrate in said peripheral circuit region; forming a first sidewall insulation film on sidewalls of said first gate electrode in said memory cell array region and a second sidewall insulation film on sidewalls of said second gate electrode in said peripheral circuit region; forming a first impurity region in the memory cell array region and a second impurity region in the peripheral circuit region by implanting impurity ions with said first and second sidewall insulation films as a mask; forming a conductive layer and a first insulation film on said first impurity region and said first sidewall insulation film in said memory cell array region, and on said second impurity region and said second sidewall insulation film in said peripheral circuit region, and patterning said conductive layer and said first insulation film into a configuration to form a first insulator layer on a first conductor layer in said memory cell array region and a second insulator layer on a second conductor layer in said peripheral circuit region; forming a second insulation film all over said semiconductor substrate and anisotropically etching the second insulation film to form a third sidewall insulation film on a sidewall of said first conductor layer and on a portion of said first sidewall insulation film formed on sidewalls of said first gate electrode in said memory cell array region, and a fourth sidewall insulation film on a sidewall of said second conductor layer and on a portion of said second sidewall insulation film formed on sidewalls of said second gate electrode in said peripheral circuit region; and forming a third impurity region in said memory cell array region and a fourth impurity region in said peripheral circuit region by diffusing the impurities introduced in a third conductive layer, formed on said third sidewall insulation film and on the semiconductor substrate, into said semiconductor substrate by heat treatment.
References Cited (Backward Citations)
JPS5539688A
Cited
JPS6037766A
Cited
JPS61156862A
Cited
JPS62114264A
Cited
JPS62124765A
Cited
US4702797A
Cited
US4978628A
Cited
JPS63294472A
Cited
JPS63318151A
Cited
JPS6480060A
Cited
EP0315422A2
Cited
US5108940A
Cited
US4871688A
Cited
DE3922456A1
Cited
US5005072A
Cited
DE4107883A1
Cited
US5364811A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-29 | 2001-03-31 | 2001-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-29 | 2005-03-31 | 2005-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-29 | 2009-03-31 | 2009-09-30 | $7700.00 | Window Closed / Lapsed |