Integrated circuit device of semiconductors

Abstract

Abstract PURPOSE:To obtain an IC of a high degree of integration suitably used for MOS memories, by laminating a MOS transistor and a capacity element consisting of a PN-junction diode having a high concentration of impurities on the upper surface and lower surface, respectively, of a flat layer of epitaxial growth. CONSTITUTION:An embedded region consisting of an N<+>-type region 3 formed by diffusing As, an N<+>-type region 5 formed in a portion of the region 3 by diffusing P, and a P<+>-type region 4 enclosing the regions 3,5 and formed by the injection of B ions is formed in a P<+>-type Si substrate 1. A P-type layer 2 is then formed by epitaxial growth on the entire surface of the substrate 1 including the regions 3,5,4. During this heat treatment, the upper and lower portions of the region 4 are expanded into the substrate 1 and layer 2, and the region 5 is also expanded deeply in the upward and downward directions. An N<+>-type drain region 6 is then formed in the layer 2 by diffusing As, and also an N<3>-type soruce region 7 is formed on the region 5. A poly-crystalline Si gate electrode is provided via an SiO2 film 8 on those portions of the layer 2 which is exposed between the regions 6,7, and these portions of the layer 2 constitute IGFT. That portion of the region 7 which is in contact at its lower surface with the region 5 is used as a capacitance region.

Inventors

• 👤 Toshio Wada

Bibliographic Details