Patent US5671229A successfully refreshed from Google Patents.
US5671229A
Expired / Lapsed
US
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Flash eeprom system with defect handling
Assignee: SanDisk Technologies LLC
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Filing: 1994-05-25
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Granted: 1997-09-23
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Expires: 2014-05-25
Abstract
Abstract A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.
Inventors
- 👤 Eliyahou Harari
- 👤 Robert D. Norman
- 👤 Sanjay Mehrotra
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 23:36
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/26; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/023; G06F12/0238; G06F12/0246; G06F12/08; G06F12/0802; G06F12/0804; G06F12/0866; G06F12/0875; G06F12/12; G06F12/121; G06F12/123; G06F3/00; G06F3/06; G06F3/0601; G06F3/0602; G06F3/0614; G06F3/0616; G06F3/0628; G06F3/0638; G06F3/064; G06F3/0646; G06F3/0652; G06F3/0668; G06F3/0671; G06F3/0673; G06F3/0679; G06F3/068; G06F3/0683; G06F3/0688; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5635; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14; G11C16/16; G11C16/34; G11C16/3436; G11C16/344; G11C16/3445; G11C16/3454; G11C16/3459; G11C29/52; G11C29/70; G11C29/76; G11C29/765; G11C29/78; G11C29/80; G11C29/816; G11C29/82; G11C7/00; G11C7/10; G11C7/1015; G11C7/1039; G11C8/00; G11C8/12; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1068; G06F2212/00; G06F2212/20; G06F2212/202; G06F2212/2022; G06F2212/31; G06F2212/312; G06F2212/72; G06F2212/7201; G06F2212/7203; G06F2212/7205; G06F2212/7207; G06F2212/7208; G06F3/0662; G06F3/0664; G11C2211/00; G11C2211/56; G11C2211/562; G11C2211/5621; G11C2211/563; G11C2211/5634; G11C2211/564; G11C2211/5643; G11C2216/00; G11C2216/12; G11C2216/18; G11C29/30; G11C29/34
Claims Analysis
Total Claims: 39
Claim 1
Independent Claim
106 words
A fault-tolerant memory system, comprising: an array of flash EEPROM Cells; redundant cells within the array; a memory controller coupled to the array for controlling memory operations of the array; error detection means operated with said memory controller during use of the memory, for detecting a defect and its address within the array; a defect map maintained by said memory controller during use of the memory and stored within the array for storing the address of said detected defect; and defective cell substituting means operated with said memory controller responsive to said defect map for substituting said detected defect with a corresponding number of redundant cells.
Claim 2
Dependent Claim
106 words
A fault-tolerant memory system, comprising: an array of flash EEPROM Cells; redundant cells within the array; a memory controller coupled to the array for controlling memory operations of the array; error detection means operated with said memory controller during use of the memory, for detecting a defect and its address within the array; a defect map maintained by said memory controller during use of the memory and stored within the array for storing the address of said detected defect; and defective cell substituting means operated with said memory controller responsive to said defect map for substituting said detected defect with a corresponding number of redundant cells.
Claim 3
Dependent Claim
134 words
A fault-tolerant memory system, comprising: an array of flash EEPROM cells; a plurality of Flash erasable sectors partitioned from said array such that all cells within each sector are erasable together; redundant cells within said array for substituting one or more defective cells; a memory controller coupled to the array for controlling memory operations of the array; error detection means operated with said memory controller during use of the memory for detecting one or more defective cells within a given sector; a defect map maintained by said memory controller during use of the memory and stored within the array for storing addresses of said detected one or more defective cells; and defective cell substituting means for substituting said one or more defective cells within a given sector with a corresponding number of redundant cells.
Claim 4
Dependent Claim
134 words
A fault-tolerant memory system, comprising: an array of flash EEPROM cells; a plurality of Flash erasable sectors partitioned from said array such that all cells within each sector are erasable together; redundant cells within said array for substituting one or more defective cells; a memory controller coupled to the array for controlling memory operations of the array; error detection means operated with said memory controller during use of the memory for detecting one or more defective cells within a given sector; a defect map maintained by said memory controller during use of the memory and stored within the array for storing addresses of said detected one or more defective cells; and defective cell substituting means for substituting said one or more defective cells within a given sector with a corresponding number of redundant cells.
Claim 5
Dependent Claim
29 words
A fault-tolerant memory system, as in claim 2, wherein a defect map for storing an address of a defective cell is stored in the sector containing the defective cell.
Claim 6
Dependent Claim
37 words
A fault-tolerant memory system as in claim 2, wherein said redundant cells are in the same sector as said given sector when the one or more defective cells in the sector do not exceed a predetermined number.
Claim 7
Dependent Claim
35 words
A fault-tolerant memory system as in claim 2, wherein said redundant cells are in a different sector from said given sector when the one or more defective cells in the sector exceed a predetermined number.
Claim 8
Independent Claim
127 words
A system for correcting errors from defective cells within an array of Flash EEprom cells, comprising: a plurality of Flash erasable sectors partitioned from said array such that all cells within each sector are erasable together; redundant cells within said array for substituting one or more defective cells; error detection means for detecting one or more defective cells within a given sector; defective cell substituting means for substituting said one or more defective cells within a given sector with a corresponding number of redundant cells; and wherein said redundant cells are in the same sector as the defective cells when the defective cells in the sector do not exceed a predetermined number, and said redundant cells are in a different sector when said predetermined number is exceeded.
Claim 9
Independent Claim
127 words
A system for correcting errors from defective cells within an array of Flash EEprom cells, comprising: a plurality of Flash erasable sectors partitioned from said array such that all cells within each sector are erasable together; redundant cells within said array for substituting one or more defective cells; error detection means for detecting one or more defective cells within a given sector; defective cell substituting means for substituting said one or more defective cells within a given sector with a corresponding number of redundant cells; and wherein said redundant cells are in the same sector as the defective cells when the defective cells in the sector do not exceed a predetermined number, and said redundant cells are in a different sector when said predetermined number is exceeded.
Claim 10
Dependent Claim
36 words
A system for correcting errors from defective cells within an array of Flash EEprom cells as in claim 6, wherein said sector is replaced in its entirety by a redundant sector when said number is exceeded.
Claim 11
Dependent Claim
36 words
A system for correcting errors from defective cells within an array of Flash EEprom cells as in claim 6, wherein said system for correcting errors applies whenever a defective cell arises during operations of the array.
Claim 12
Dependent Claim
32 words
A system for correcting errors from defective cells within an array of Flash EEprom cells as in claim 8, further comprising error correction codes for detecting and correcting errors from defective cells.
Claim 13
Dependent Claim
131 words
A fault-tolerant memory system for correcting bad data in defective cells within an array of Flash EEprom cells, comprising: redundant cells within the array for storing good data intended for the defective cells; a memory controller coupled to the array for controlling memory operations of the array; error detection means operated with said memory controller during use of the memory for detecting a defect and its address within the array; a defect map maintained by said memory controller during use of the memory and stored within the array for storing the address of said detected defect; and data substituting means operated with said memory controller and responsive to said defect map for substituting the bad data in said detected defect with the good data in a corresponding number of redundant cells.
Claim 14
Dependent Claim
131 words
A fault-tolerant memory system for correcting bad data in defective cells within an array of Flash EEprom cells, comprising: redundant cells within the array for storing good data intended for the defective cells; a memory controller coupled to the array for controlling memory operations of the array; error detection means operated with said memory controller during use of the memory for detecting a defect and its address within the array; a defect map maintained by said memory controller during use of the memory and stored within the array for storing the address of said detected defect; and data substituting means operated with said memory controller and responsive to said defect map for substituting the bad data in said detected defect with the good data in a corresponding number of redundant cells.
Claim 15
Dependent Claim
52 words
A fault-tolerant memory system for correcting bad data in defective cells within an array of Flash EEprom cells as in claim 10, further comprising means for automatically saving the good data intended to be written to said detected defect to the corresponding redundant cells, thereby preserving the integrity of the good data.
Claim 16
Dependent Claim
40 words
A fault-tolerant memory system for correcting bad data in defective cells within an array of Flash EEprom cells as in claim 11, wherein said system for correcting errors applies whenever a defective cell arises during memory operations of the array.
Claim 17
Independent Claim
162 words
A system for correcting bad data in defective cells within an array of Flash EEprom cells, comprising: redundant cells within the array for storing good data intended for the defective cells; a memory controller coupled to the array for controlling memory operations of the array; error detection means operated with said memory controller for detecting any defective cells within the array; a defect map maintained by said memory controller and stored within the array for storing addressess of defective cells; data substituting means operated with said memory controller and responsive to said defect map for substituting the bad data in a detected cell with the good data in a corresponding redundant cell; means for automatically saving the good data intended to be written to the defective cells to the corresponding redundant cells, thereby preserving the integrity of the good data; and said array being partitioned into a plurality of Flash erasable sectors such that all cells within each sector are erasable together.
Claim 18
Independent Claim
162 words
A system for correcting bad data in defective cells within an array of Flash EEprom cells, comprising: redundant cells within the array for storing good data intended for the defective cells; a memory controller coupled to the array for controlling memory operations of the array; error detection means operated with said memory controller for detecting any defective cells within the array; a defect map maintained by said memory controller and stored within the array for storing addressess of defective cells; data substituting means operated with said memory controller and responsive to said defect map for substituting the bad data in a detected cell with the good data in a corresponding redundant cell; means for automatically saving the good data intended to be written to the defective cells to the corresponding redundant cells, thereby preserving the integrity of the good data; and said array being partitioned into a plurality of Flash erasable sectors such that all cells within each sector are erasable together.
Claim 19
Independent Claim
180 words
A system for correcting bad data in defective cells within an array of Flash EEprom cells, comprising: redundant cells within the array for storing good data intended for the defective cells; a memory controller coupled to the array for controlling memory operations of the array; error detection means operated with said memory controller for detecting any defective cells within the array; a defect map maintained by said memory controller and stored within the array for storing addresses of defective cells; data substituting means operated with said memory controller and responsive to said defect map for substituting the bad data in a detected defective cell with the good data in a corresponding redundant cell; means for automatically saving the good data intended to be written to the defective cells to the corresponding redundant cells thereby preserving the integrity of the good data; and said array is partitioned into a plurality of Flash erasable sectors such that all cells within each sector are erasable together, and each sector has redundant cells therein for substituting defective cells that arise in said each sector.
Claim 20
Independent Claim
180 words
A system for correcting bad data in defective cells within an array of Flash EEprom cells, comprising: redundant cells within the array for storing good data intended for the defective cells; a memory controller coupled to the array for controlling memory operations of the array; error detection means operated with said memory controller for detecting any defective cells within the array; a defect map maintained by said memory controller and stored within the array for storing addresses of defective cells; data substituting means operated with said memory controller and responsive to said defect map for substituting the bad data in a detected defective cell with the good data in a corresponding redundant cell; means for automatically saving the good data intended to be written to the defective cells to the corresponding redundant cells thereby preserving the integrity of the good data; and said array is partitioned into a plurality of Flash erasable sectors such that all cells within each sector are erasable together, and each sector has redundant cells therein for substituting defective cells that arise in said each sector.
Claim 21
Independent Claim
180 words
A system for correcting bad data in defective cells within an array of Flash EEprom cells, comprising: redundant cells within the array for storing good data intended for the defective cells; a memory controller coupled to the array for controlling memory operations of the array; error detection means operated with said memory controller for detecting any defective cells within the array; a defect map maintained by said memory controller and stored within the array for storing addresses of defective cells; data substituting means operated with said memory controller and responsive to said defect map for substituting the bad data in a detected defective cell with the good data in a corresponding redundant cell; means for automatically saving the good data intended to be written to the defective cells to the corresponding redundant cells thereby preserving the integrity of the good data; and said array being partitioned into a plurality of Flash erasable sectors such that all cells within each sector are erasable together, wherein the defect map for a defective cell is stored in a sector containing the defective cell.
Claim 22
Independent Claim
180 words
A system for correcting bad data in defective cells within an array of Flash EEprom cells, comprising: redundant cells within the array for storing good data intended for the defective cells; a memory controller coupled to the array for controlling memory operations of the array; error detection means operated with said memory controller for detecting any defective cells within the array; a defect map maintained by said memory controller and stored within the array for storing addresses of defective cells; data substituting means operated with said memory controller and responsive to said defect map for substituting the bad data in a detected defective cell with the good data in a corresponding redundant cell; means for automatically saving the good data intended to be written to the defective cells to the corresponding redundant cells thereby preserving the integrity of the good data; and said array being partitioned into a plurality of Flash erasable sectors such that all cells within each sector are erasable together, wherein the defect map for a defective cell is stored in a sector containing the defective cell.
Claim 23
Independent Claim
176 words
A system for correcting bad data in defective cells within an array of Flash EEprom cells, comprising: redundant cells within the array for storing good data intended for the defective cells; a memory controller coupled to the array for controlling memory operations of the array; error detection means operated with said memory controller for detecting any defective cells within the array; a defect map maintained by said memory controller and stored within the array for storing addresses of defective cells; data substituting means operated with said memory controller and responsive to said defect map for substituting the bad data in a detected defective cell with the good data in a corresponding redundant cell; and said array being partitioned into a plurality of Flash erasable sectors such that all cells within each sector are erasable together, wherein said redundant cells are in the same sector as the defective cells when the defective cells in the sector do not exceed a predetermined number, and said redundant cells are in a different sector when said predetermined number is exceeded.
Claim 24
Independent Claim
176 words
A system for correcting bad data in defective cells within an array of Flash EEprom cells, comprising: redundant cells within the array for storing good data intended for the defective cells; a memory controller coupled to the array for controlling memory operations of the array; error detection means operated with said memory controller for detecting any defective cells within the array; a defect map maintained by said memory controller and stored within the array for storing addresses of defective cells; data substituting means operated with said memory controller and responsive to said defect map for substituting the bad data in a detected defective cell with the good data in a corresponding redundant cell; and said array being partitioned into a plurality of Flash erasable sectors such that all cells within each sector are erasable together, wherein said redundant cells are in the same sector as the defective cells when the defective cells in the sector do not exceed a predetermined number, and said redundant cells are in a different sector when said predetermined number is exceeded.
Claim 25
Dependent Claim
37 words
A system for correcting bad data in defective cells within an array of Flash EEprom cells as in claim 16, wherein said sector is replaced in its entirety by a redundant sector when said number is exceeded.
Claim 26
Dependent Claim
37 words
A system for correcting bad data in defective cells within an array of Flash EEprom cells as in claim 16, wherein the data substituting means applies whenever a defective cell arises during memory operations of the array.
Claim 27
Dependent Claim
33 words
A system for correcting bad data in defective cells within an array of Flash EEprom cells as in claim 18, further comprising error correction codes for detecting and correcting errors from defective cells.
Claim 28
Dependent Claim
150 words
A fault-tolerant memory system, comprising: an array of flash EEPROM cells; a memory controller coupled to the array for controlling memory operations of the array; error detection means operated with said memory controller during use of the memory for detecting a defect within the array, said detected defect comprising at least one defective cell; redundant cells within the array for substituting said at least one defective cell; defective cell mapping means operated with said memory controller for mapping said at least one defective cell to a corresponding redundant cell substituting therefor; a defect map maintained by said memory controller during use of the memory and stored within the array for storing information related to the mapping of said at least one defective cell to the corresponding redundant cell, such that when said detected defect is being accessed, said memory controller, responsive to said defect map, accesses the corresponding redundant cell.
Claim 29
Dependent Claim
150 words
A fault-tolerant memory system, comprising: an array of flash EEPROM cells; a memory controller coupled to the array for controlling memory operations of the array; error detection means operated with said memory controller during use of the memory for detecting a defect within the array, said detected defect comprising at least one defective cell; redundant cells within the array for substituting said at least one defective cell; defective cell mapping means operated with said memory controller for mapping said at least one defective cell to a corresponding redundant cell substituting therefor; a defect map maintained by said memory controller during use of the memory and stored within the array for storing information related to the mapping of said at least one defective cell to the corresponding redundant cell, such that when said detected defect is being accessed, said memory controller, responsive to said defect map, accesses the corresponding redundant cell.
Claim 30
Independent Claim
154 words
A method of handling defects within an array of Flash EEprom cells, comprising the steps of: providing a memory controller coupled to the array for controlling memory operations of the array; using said memory controller to detect a defect within the array during use of the memory, said detected defect comprising at least one defective cell; providing redundant cells within the array for substituting said at least one defective cell; using said memory controller to map said at least one defective cell to a corresponding redundant cell substituting therefor; using said memory controller during use of the memory to maintain a defect map and storing said defect map within the array, said defect map storing information related to the mapping of said at least one defective cell to the corresponding redundant cell, such that when said detected defect is being accessed, said memory controller, responsive to said defect map, accesses the corresponding redundant cell.
Claim 31
Independent Claim
154 words
A method of handling defects within an array of Flash EEprom cells, comprising the steps of: providing a memory controller coupled to the array for controlling memory operations of the array; using said memory controller to detect a defect within the array during use of the memory, said detected defect comprising at least one defective cell; providing redundant cells within the array for substituting said at least one defective cell; using said memory controller to map said at least one defective cell to a corresponding redundant cell substituting therefor; using said memory controller during use of the memory to maintain a defect map and storing said defect map within the array, said defect map storing information related to the mapping of said at least one defective cell to the corresponding redundant cell, such that when said detected defect is being accessed, said memory controller, responsive to said defect map, accesses the corresponding redundant cell.
Claim 32
Dependent Claim
152 words
A fault-tolerant memory system, comprising: an array of flash EEPROM cells; a plurality of Flash erasable sectors being partitioned in said array such that all cells within each sector are erasable together; a memory controller coupled to the array for controlling memory operations of the array; detection means operated with said memory controller during use of the memory for detecting an error condition within a first sector containing data; sector mapping means operated with said memory controller in response to said error condition during memory operations for mapping said data in first sector to a corresponding second sector substituting therefor; and a map maintained by said memory controller during use of the memory and stored within the array for holding information related to the mapping of said data to the corresponding second sector, such that when said data is being accessed, responsive to said map the corresponding second sector is being accessed.
Claim 33
Dependent Claim
152 words
A fault-tolerant memory system, comprising: an array of flash EEPROM cells; a plurality of Flash erasable sectors being partitioned in said array such that all cells within each sector are erasable together; a memory controller coupled to the array for controlling memory operations of the array; detection means operated with said memory controller during use of the memory for detecting an error condition within a first sector containing data; sector mapping means operated with said memory controller in response to said error condition during memory operations for mapping said data in first sector to a corresponding second sector substituting therefor; and a map maintained by said memory controller during use of the memory and stored within the array for holding information related to the mapping of said data to the corresponding second sector, such that when said data is being accessed, responsive to said map the corresponding second sector is being accessed.
Claim 34
Dependent Claim
44 words
A fault-tolerant memory system as in claim 22, wherein: each sector has redundant cells therein for substituting defective cells that arise in said each sector; and said first sector is being substituted by said second sector when the defective cells exceed a predetermined number.
Claim 35
Independent Claim
139 words
A method of handling defects within an array of Flash EEPROM cells, comprising the steps of: partitioning said array into a plurality of Flash erasable sectors such that all cells within each sector are erasable together; controlling memory operations of the array, the memory operations including normal operations such as erasing, programming and reading of data in the array; detecting an error condition within a first sector during a normal operation of the array; mapping in response to said error condition said first sector to a corresponding second sector substituting therefor; maintaining and storing a map within the array during normal operations for holding information related to the mapping of said first sector to the corresponding second sector; and subsequently causing the second sector to be accessed instead of said first sector whenever said first sector is being accessed.
Claim 36
Independent Claim
139 words
A method of handling defects within an array of Flash EEPROM cells, comprising the steps of: partitioning said array into a plurality of Flash erasable sectors such that all cells within each sector are erasable together; controlling memory operations of the array, the memory operations including normal operations such as erasing, programming and reading of data in the array; detecting an error condition within a first sector during a normal operation of the array; mapping in response to said error condition said first sector to a corresponding second sector substituting therefor; maintaining and storing a map within the array during normal operations for holding information related to the mapping of said first sector to the corresponding second sector; and subsequently causing the second sector to be accessed instead of said first sector whenever said first sector is being accessed.
Claim 37
Dependent Claim
52 words
A method of handling defects within an array of Flash EEPROM cells as in claim 24, wherein: each sector has redundant cells therein for substituting defective cells that arise in said each sector; and said first sector is being substituted by said second sector when the defective cells exceed a predetermined number.
Claim 38
Independent Claim
125 words
A method of handling defects within an array of Flash EEPROM cells, comprising the steps of: partitioning said array into a plurality of Flash erasable sectors such that all cells within each sector are erasable together; providing redundant cells within each sector for substituting defective cells; coupling a memory controller to the array for controlling memory operations of the array; detecting one or more defective cells within a given sector with said memory controller during use of the memory; maintaining a defect map of addresses of said defected one or more defective cells during use of the memory; storing said defect map within the array; and substituting said detected one or more defective cells within a given sector with a corresponding number of redundant cells.
Claim 39
Independent Claim
125 words
A method of handling defects within an array of Flash EEPROM cells, comprising the steps of: partitioning said array into a plurality of Flash erasable sectors such that all cells within each sector are erasable together; providing redundant cells within each sector for substituting defective cells; coupling a memory controller to the array for controlling memory operations of the array; detecting one or more defective cells within a given sector with said memory controller during use of the memory; maintaining a defect map of addresses of said defected one or more defective cells during use of the memory; storing said defect map within the array; and substituting said detected one or more defective cells within a given sector with a corresponding number of redundant cells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-22 | 2001-03-24 | 2001-09-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-22 | 2005-03-24 | 2005-09-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-22 | 2009-03-24 | 2009-09-23 | $7700.00 | Window Closed / Lapsed |