Method and apparatus for detecting and selecting voltage supplies for flash memory

Claim 2

An integrated circuit comprising: a first circuit; a first conductor for coupling to a first external supply voltage; a second conductor for coupling to a second external supply voltage; a first internal supply operative to output a first internal supply voltage; a second internal supply operative to output a second internal supply voltage; a first switch coupled between the first conductor and the first circuit; a second switch coupled between the second conductor and the first circuit; a third switch coupled between the first internal supply and the first circuit; a fourth switch coupled between the second internal supply and the first circuit; and a control circuit coupled to the switches, the control circuit selectively switching on only one of the first and third switches in response to the voltage level of the first external supply voltage and selectively switching on only one of the second and fourth switches in response to the voltage level of the second external supply voltage.

Claim 3

The integrated circuit of claim 1, wherein the means further comprises: a first voltage detection circuit for coupling to the first external supply voltage, the first voltage detection circuit being operative to output a first signal indicating whether the first external supply voltage exceeds a first threshold voltage, wherein the control circuit switches the first switch on and the third switch off if the first signal indicates that the first external supply voltage exceeds the first threshold voltage; and a second voltage detection circuit for coupling to the second external supply voltage, the second voltage detection circuit being operative to output a second signal indicating whether the second external supply voltage exceeds a second threshold voltage, wherein the control circuit switches the second switch on and the fourth switch off if the second signal indicates that the second external supply voltage exceeds the second threshold voltage.

Claim 4

A nonvolatile memory device comprising: an array of memory cells; a first conductor for coupling to an external operating supply voltage; a second conductor for coupling to an external programming supply voltage; a first internal supply operative to output an internal operating supply voltage; a second internal supply operative to output an internal programming supply voltage; a first switch coupled between the first conductor and the array of memory cells; a second switch coupled between the second conductor and the array of memory cells; a third switch coupled between the first internal supply and the array of memory cells; a fourth switch coupled between the second internal supply and the array of memory cells; and a control circuit coupled to the switches, the control circuit for switching on a one of the first and third switches in response to the voltage level of the external operating supply voltage, and for switching on a one of the second and fourth switches in response to the voltage level of the external programming supply voltage.

Claim 5

A nonvolatile memory device comprising: an array of memory cells; a first conductor for coupling to an external operating supply voltage; a second conductor for coupling to an external programming supply voltage; a first internal supply operative to output an internal operating supply voltage; a second internal supply operative to output an internal programming supply voltage; a first switch coupled between the first conductor and the array of memory cells; a second switch coupled between the second conductor and the array of memory cells; a third switch coupled between the first internal supply and the array of memory cells; a fourth switch coupled between the second internal supply and the array of memory cells; and a control circuit coupled to the switches, the control circuit for switching on a one of the first and third switches in response to the voltage level of the external operating supply voltage, and for switching on a one of the second and fourth switches in response to the voltage level of the external programming supply voltage.

Claim 6

The nonvolatile memory device of claim 3, further comprising: a first voltage detection circuit for coupling to the external operating supply voltage, the first voltage detection circuit being operative to output a first signal indicating whether the external operating supply voltage exceeds a first threshold voltage, wherein the control circuit switches the first switch on and the third switch off if the first signal indicates that the external operating supply voltage exceeds the first threshold voltage; and a second voltage detection circuit for coupling to the external programming supply voltage, the second voltage detection circuit being operative to output a second signal indicating whether the external programming supply voltage exceeds a second threshold voltage, wherein the control circuit switches the second switch on and the fourth switch off if the second signal indicates that the external programming supply voltage exceeds the second threshold voltage.

Claim 7

A nonvolatile memory device comprising: a first conductor coupled to an external operating supply voltage; a first switch coupled between the first conductor and an array of memory cells; a second conductor coupled to an external programming supply voltage; a second switch coupled between the second conductor and the array of memory cells; a first internal power supply for providing an internal operating supply voltage at a first voltage level; a third switch coupled between the first internal supply and the array of memory cells; a second internal power supply for providing an internal programming supply voltage at a second voltage level; a fourth switch coupled between the second internal supply and the array of memory cells; a first voltage detector circuit coupled to the first conductor for outputting a first signal that indicates whether the external operating supply voltage is at the first voltage level; a second voltage detector circuit coupled of the second conductor for outputting a second signal that indicates whether the external programming supply voltage is at the second voltage level; and a control circuit coupled to the first and second voltage detector circuits and to the switches, the control circuit for controlling the first and third switches to couple the first conductor to the array of memory cells and to decouple the first internal power supply from the array of memory cells if the external operating supply voltage is at the first voltage level, for controlling the first and third switches to decouple the first conductor to the array of memory cells and to couple the first internal power supply from the array of memory cells if the external operating supply voltage is less than the first voltage level, for controlling the second and fourth switches to couple the second conductor to the array of memory cells and to decouple the second internal power supply from the array of memory cells if the external programming supply voltage is at the second voltage level, and for controlling the second and fourth switches to decouple the second conductor to the array of memory cells and to couple the second internal power supply from the array of memory cells if the external programming supply voltage is less than the second voltage level.

Claim 8

A nonvolatile memory device comprising: a first conductor coupled to an external operating supply voltage; a first switch coupled between the first conductor and an array of memory cells; a second conductor coupled to an external programming supply voltage; a second switch coupled between the second conductor and the array of memory cells; a first internal power supply for providing an internal operating supply voltage at a first voltage level; a third switch coupled between the first internal supply and the array of memory cells; a second internal power supply for providing an internal programming supply voltage at a second voltage level; a fourth switch coupled between the second internal supply and the array of memory cells; a first voltage detector circuit coupled to the first conductor for outputting a first signal that indicates whether the external operating supply voltage is at the first voltage level; a second voltage detector circuit coupled of the second conductor for outputting a second signal that indicates whether the external programming supply voltage is at the second voltage level; and a control circuit coupled to the first and second voltage detector circuits and to the switches, the control circuit for controlling the first and third switches to couple the first conductor to the array of memory cells and to decouple the first internal power supply from the array of memory cells if the external operating supply voltage is at the first voltage level, for controlling the first and third switches to decouple the first conductor to the array of memory cells and to couple the first internal power supply from the array of memory cells if the external operating supply voltage is less than the first voltage level, for controlling the second and fourth switches to couple the second conductor to the array of memory cells and to decouple the second internal power supply from the array of memory cells if the external programming supply voltage is at the second voltage level, and for controlling the second and fourth switches to decouple the second conductor to the array of memory cells and to couple the second internal power supply from the array of memory cells if the external programming supply voltage is less than the second voltage level.

Claim 9

An integrated circuit comprising: an array of memory cells; a conductor coupled to an external supply voltage; a voltage ramp detector circuit coupled to the first conductor for outputting a signal indicating when the external supply voltage exceeds a ramp voltage; an internal power supply operative to output an internal supply voltage; a first switch coupled between the first conductor and the array of memory cells; a second switch coupled between the first internal supply and the array of memory cells; and a control circuit coupled to the switches, the control circuit for switching on a one of the first and second switches in response to the voltage level of the external operating supply voltage, wherein the control circuit causes the first switch to initially couple the first internal supply to the array of memory cells until the external operating supply voltage exceeds the ramp voltage, and wherein the control circuit thereafter selectively causes the second switch to couple a one of the external operating supply voltage and the internal operating supply voltage to the array of memory cells in response to a voltage level of the external supply voltage.

Claim 10

An integrated circuit comprising: an array of memory cells; a conductor coupled to an external supply voltage; a voltage ramp detector circuit coupled to the first conductor for outputting a signal indicating when the external supply voltage exceeds a ramp voltage; an internal power supply operative to output an internal supply voltage; a first switch coupled between the first conductor and the array of memory cells; a second switch coupled between the first internal supply and the array of memory cells; and a control circuit coupled to the switches, the control circuit for switching on a one of the first and second switches in response to the voltage level of the external operating supply voltage, wherein the control circuit causes the first switch to initially couple the first internal supply to the array of memory cells until the external operating supply voltage exceeds the ramp voltage, and wherein the control circuit thereafter selectively causes the second switch to couple a one of the external operating supply voltage and the internal operating supply voltage to the array of memory cells in response to a voltage level of the external supply voltage.

Claim 11

The integrated circuit of claim 6 further comprising: a voltage detection circuit coupled to the external supply voltage, the voltage detection circuit being operative to output a first signal indicating whether the external supply voltage exceeds a threshold voltage, wherein the control circuit switches the first switch on and the second switch off if the first signal indicates that the external supply voltage exceeds the threshold voltage.