Precision voltage reference

Claim 2

A precision voltage reference circuit comprising a pair of similar flash EEPROM memory cells each having a source, drain, floating gate, and control gate, each of the pair of similar flash EEPROM memory cells having a different charge on its floating gate; means for connecting each of said cells in a pair of parallel circuits in which equal current values are generated in an equilibrium condition; means responsive to currents in the pair of parallel circuits for providing an output voltage which may be used as a reference value when the currents are in equilibrium; and means for sensing variations in the output voltage to vary the current through the flash EEPROM memory cells to bring the currents into equilibrium when the output voltage varies from the voltage provided at equilibrium.

Claim 3

A precision voltage reference circuit as claimed in claim 1 in which the means for sensing variations in the output voltage to vary the current through the flash EEPROM memory cells to bring the currents into equilibrium when the output voltage varies from the voltage provided at equilibrium comprises: resistive means arranged to provide a voltage divider network, and means for sensing the voltage at different points of the voltage divider network to furnish control gate voltages for the flash EEPROM memory cells.

Claim 4

A precision voltage reference circuit as claimed in claim 2 in which the resistive means comprises P type FET devices with source and drain terminals connected in series between the output voltage and a second level of potential and having gate terminals connected to drain terminals.

Claim 5

A precision voltage reference circuit as claimed in claim 1 in which the means responsive to currents in the pair of parallel circuits for providing an output voltage which may be used as a reference value when the currents are in equilibrium comprises a differential amplifier, and means for providing voltages indicative of the currents in the pair of parallel circuits as inputs to the differential amplifier.

Claim 6

A precision voltage reference circuit comprising a pair of similar flash EEPROM memory cells each having a source, drain, floating gate, and control gate, each of the pair of similar flash EEPROM memory cells having a different charge on its floating gate; means for connecting each of said cells in a pair of parallel circuits in which equal current values are generated in an equilibrium condition; means responsive to currents in the pair of parallel circuits for providing an output voltage which may be used as a reference value which the currents are in equilibrium; and means for sensing variations in the output voltage to vary the current through the flash EEPROM memory cells to bring the currents into equilibrium when the output voltage varies from the voltage provided at equilibrium; and in which the means for connecting each of said cells in a pair of parallel circuits in which equal current values are generated in an equilibrium condition comprises means for mirroring current in a first one of the parallel current paths through a portion of a second one of the current paths, and in which the means responsive to currents in the pair of parallel circuits for providing an output voltage which may be used as a reference value when the currents are in equilibrium comprises means for sensing the difference between the mirrored current and current through the flash EEPROM memory cell of the second one of the memory paths to vary the output voltage.

Claim 7

A precision voltage reference circuit comprising a pair of similar flash EEPROM memory cells each having a source, drain, floating gate, and control gate, each of the pair of similar flash EEPROM memory cells having a different charge on its floating gate; means for connecting each of said cells in a pair of parallel circuits in which equal current values are generated in an equilibrium condition; means responsive to currents in the pair of parallel circuits for providing an output voltage which may be used as a reference value which the currents are in equilibrium; and means for sensing variations in the output voltage to vary the current through the flash EEPROM memory cells to bring the currents into equilibrium when the output voltage varies from the voltage provided at equilibrium; and in which the means for connecting each of said cells in a pair of parallel circuits in which equal current values are generated in an equilibrium condition comprises means for mirroring current in a first one of the parallel current paths through a portion of a second one of the current paths, and in which the means responsive to currents in the pair of parallel circuits for providing an output voltage which may be used as a reference value when the currents are in equilibrium comprises means for sensing the difference between the mirrored current and current through the flash EEPROM memory cell of the second one of the memory paths to vary the output voltage.

Claim 8

A precision voltage reference circuit as claimed in claim 5 further comprising means for initializing the currents through the pair of parallel paths at selected equilibrium current values.

Claim 9

A precision voltage reference circuit as claimed in claim 5 further comprising means for biasing the reference circuit to function with at least two different source voltages.

Claim 10

A precision voltage reference circuit as claimed in claim 7 in which the means for biasing the reference circuit to function with at least two different source voltages comprises charge pump means for selectively providing an output voltage greater than voltages furnished by either of the two different source voltages.

Claim 11

A computer system comprising: central processing means; bus means; main memory means; and means for providing programmable non-volatile long term storage, the last mentioned means including means for providing a precision voltage reference comprising a pair of similar flash EEPROM memory cells, means for connecting each of said cells in a pair of parallel circuits in which equal current values are generated in an equilibrium condition, means responsive to currents in the pair of parallel circuits for providing an output voltage which may be used as a reference value when the currents are in equilibrium, and means for sensing variations in the output voltage to vary the current through the flash EEPROM memory cells to bring the currents into equilibrium when the output voltage varies from the voltage provided at equilibrium.

Claim 12

A computer system comprising: central processing means; bus means; main memory means; and means for providing programmable non-volatile long term storage, the last mentioned means including means for providing a precision voltage reference comprising a pair of similar flash EEPROM memory cells, means for connecting each of said cells in a pair of parallel circuits in which equal current values are generated in an equilibrium condition, means responsive to currents in the pair of parallel circuits for providing an output voltage which may be used as a reference value when the currents are in equilibrium, and means for sensing variations in the output voltage to vary the current through the flash EEPROM memory cells to bring the currents into equilibrium when the output voltage varies from the voltage provided at equilibrium.

Claim 13

A computer system comprising: central processing means; bus means; main memory means; and means for providing programmable non-volatile long term storage, the last mentioned means including means for providing a precision voltage reference comprising a pair of similar flash EEPROM memory cells, means for connecting each of said cells in a pair of parallel circuits in which equal current values are generated in an equilibrium condition, means responsive to currents in the pair of parallel circuits for providing an output voltage which may be used as a reference value when the currents are in equilibrium, means for sensing variations in the output voltage to vary the current through the flash EEPROM memory cells to bring the currents into equilibrium when the output voltage varies from the voltage provided at equilibrium, and in which the means for providing a precision voltage reference further comprises voltage pump means for generating a voltage sufficient to allow an output voltage which may be used as a reference value of a value sufficient for use with flash EEPROM devices to be established.

Claim 14

A computer system comprising: central processing means; bus means; main memory means; and means for providing programmable non-volatile long term storage, the last mentioned means including means for providing a precision voltage reference comprising a pair of similar flash EEPROM memory cells, means for connecting each of said cells in a pair of parallel circuits in which equal current values are generated in an equilibrium condition, means responsive to currents in the pair of parallel circuits for providing an output voltage which may be used as a reference value when the currents are in equilibrium, means for sensing variations in the output voltage to vary the current through the flash EEPROM memory cells to bring the currents into equilibrium when the output voltage varies from the voltage provided at equilibrium, and in which the means for providing a precision voltage reference further comprises voltage pump means for generating a voltage sufficient to allow an output voltage which may be used as a reference value of a value sufficient for use with flash EEPROM devices to be established.

Claim 15

A computer system comprising: central processing means; bus means; main memory means; and means for providing programmable non-volatile long term storage, the last mentioned means including means for providing a precision voltage reference comprising a pair of similar flash EEPROM memory cells, means for connecting each of said cells in a pair of parallel circuits in which equal current values are generated in an equilibrium condition, means responsive to currents in the pair of parallel circuits for providing an output voltage which may be used as a reference value when the currents are in equilibrium, means for sensing variations in the output voltage to vary the current through the flash EEPROM memory cells to bring the currents into equilibrium when the output voltage varies from the voltage provided at equilibrium, and in which the means for providing a precision voltage reference further comprises means for biasing whereby the means for providing a precision voltage reference operates with a plurality of different source voltages.

Claim 16

A computer system comprising: central processing means; bus means; main memory means; and means for providing programmable non-volatile long term storage, the last mentioned means including means for providing a precision voltage reference comprising a pair of similar flash EEPROM memory cells, means for connecting each of said cells in a pair of parallel circuits in which equal current values are generated in an equilibrium condition, means responsive to currents in the pair of parallel circuits for providing an output voltage which may be used as a reference value when the currents are in equilibrium, means for sensing variations in the output voltage to vary the current through the flash EEPROM memory cells to bring the currents into equilibrium when the output voltage varies from the voltage provided at equilibrium, and in which the means for providing a precision voltage reference further comprises means for biasing whereby the means for providing a precision voltage reference operates with a plurality of different source voltages.