US5301161A
Expired / Lapsed
US
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Circuitry for power supply voltage detection and system lockout for a nonvolatile memory
Assignee: Intel Corp
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Filing: 1993-01-12
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Granted: 1994-04-05
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Expires: 2013-01-12
Abstract
Abstract A detection circuit is described that resides in a nonvolatile memory that includes a memory array and a control circuitry coupled to the memory array for controlling operations of the memory array. The detection circuit is coupled to the control circuitry and receives a power supply for detecting potential level of the power supply and for generating a reset signal to reset the control circuitry until the potential level of the power supply rises above a predetermined level. The detection circuit includes a resistor, a first, a second, and a third transistor. The first transistor has a first end coupled to receive the power supply, a second end coupled to a first node, and a third end coupled to the first node. The second transistor has a first end coupled to the first node, a second end coupled to ground, and a third end coupled to the ground. The first and second transistors function as a voltage divider. The third transistor has a first end coupled to the power supply, a second end coupled to an output node, and a third end coupled to the first node. The resistor is coupled between the output node and the ground for coupling the output node to the ground when the third transistor is not conducting, and for providing a positive potential at the output node when the third transistor is conducting. When the power supply has not reached the predetermined level, the third transistor is not conducting and the output node outputs the reset signal that is a ground potential. When the power supply rises above the predetermined level, the third transistor starts to conduct and the output node registers the positive potential and ceases generating the reset signal. The first, second, and third transistors are of the same channel type such that the circuitry operates substantially independent of process variations and temperature variations.
Inventors
- 👤 Marc E. Landgraf
- 👤 Jahanshir J. Javanifard
- 👤 Mark D. Winston
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:05
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/143; G11C16/00; G11C16/02; G11C16/06; G11C16/22; G11C16/225; G11C16/30
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
278 words
A circuitry in a nonvolatile memory for detecting a potential level of a power supply applied to the nonvolatile memory and for generating a reset signal to reset resettable circuitry in the nonvolatile memory until the potential level of the power supply rises above a predetermined voltage level, comprising: (A) a first transistor having a first end coupled to receive the power supply, a second end coupled to a first node, and a third end coupled to the first node; (B) a second transistor having a first end coupled to the first node, a second end coupled to ground, and a third end coupled to the ground, wherein the first and second transistors function as a voltage divider; (C) a third transistor having a first end coupled to the power supply, a second end coupled to an output node, a third end coupled to the first node; and (D) resistor means coupled between the output node and the ground for coupling the output node to the ground when the third transistor is not conducting, and for providing a positive potential at the output node when the third transistor is conducting, wherein when the power supply has not reached the predetermined voltage level, the third transistor is not conducting and the output node outputs the reset signal that is a ground potential, wherein when the power supply rises above the predetermined voltage level, the third transistor starts to conduct and the output node registers the positive potential and ceases generating the reset signal, wherein the first, second, and third transistors are of the same channel type such that the circuitry operates substantially independent of process variations and temperature variations.
Claim 2
Dependent Claim
278 words
A circuitry in a nonvolatile memory for detecting a potential level of a power supply applied to the nonvolatile memory and for generating a reset signal to reset resettable circuitry in the nonvolatile memory until the potential level of the power supply rises above a predetermined voltage level, comprising: (A) a first transistor having a first end coupled to receive the power supply, a second end coupled to a first node, and a third end coupled to the first node; (B) a second transistor having a first end coupled to the first node, a second end coupled to ground, and a third end coupled to the ground, wherein the first and second transistors function as a voltage divider; (C) a third transistor having a first end coupled to the power supply, a second end coupled to an output node, a third end coupled to the first node; and (D) resistor means coupled between the output node and the ground for coupling the output node to the ground when the third transistor is not conducting, and for providing a positive potential at the output node when the third transistor is conducting, wherein when the power supply has not reached the predetermined voltage level, the third transistor is not conducting and the output node outputs the reset signal that is a ground potential, wherein when the power supply rises above the predetermined voltage level, the third transistor starts to conduct and the output node registers the positive potential and ceases generating the reset signal, wherein the first, second, and third transistors are of the same channel type such that the circuitry operates substantially independent of process variations and temperature variations.
Claim 3
Dependent Claim
22 words
The circuitry of claim 1, wherein each of the first, second, and third transistors has a threshold voltage of approximately one volt.
Claim 4
Dependent Claim
23 words
The circuitry of claim 2, wherein the predetermined voltage level can be changed by changing size ratio of the first and second transistors.
Claim 5
Dependent Claim
15 words
The circuitry of claim 1, wherein the first, second, and third transistors are P-channel transistors.
Claim 6
Dependent Claim
14 words
The circuitry of claim 1, further comprising an inverter coupled to the output node.
Claim 7
Dependent Claim
13 words
The circuitry of claim 1, wherein the resistor means comprises a diffusion resistor.
Claim 8
Dependent Claim
20 words
The circuitry of claim 1, wherein the predetermined voltage level is in a range between 2 volts and 2.5 volts.
Claim 9
Dependent Claim
262 words
A circuitry in a nonvolatile memory for detecting a potential level of a power supply applied to the nonvolatile memory and for generating a reset signal to reset resettable circuitry in the nonvolatile memory until the potential level of the power supply rises above a predetermined level, comprising: (A) a first transistor having a first end coupled to receive the power supply, a second end coupled to a first node, and a third end coupled to the power supply; (B) a second transistor having a first end decoupled to the first node, a second end coupled to ground, and a third end coupled to the first node, wherein the first and second transistors function as a voltage divider; (C) a third transistor having a first end coupled to an output node, a second end coupled to the ground, a third end coupled to the first node; and (D) resistor means coupled between the output node and the power supply for providing a positive potential at the output node when the third transistor is not conducting, wherein when the powers supply has not reached the predetermined level, the third transistor is not conducting and the output node outputs the reset signal that is the positive potential, wherein when the power supply rises above the predetermined level, the third transistor starts to conduct and the output node registers a ground potential and ceases to output the reset signal, wherein the first, second, and third transistors are of the same channel type such that the circuitry operates substantially independent of process variation and temperature variation.
Claim 10
Dependent Claim
262 words
A circuitry in a nonvolatile memory for detecting a potential level of a power supply applied to the nonvolatile memory and for generating a reset signal to reset resettable circuitry in the nonvolatile memory until the potential level of the power supply rises above a predetermined level, comprising: (A) a first transistor having a first end coupled to receive the power supply, a second end coupled to a first node, and a third end coupled to the power supply; (B) a second transistor having a first end decoupled to the first node, a second end coupled to ground, and a third end coupled to the first node, wherein the first and second transistors function as a voltage divider; (C) a third transistor having a first end coupled to an output node, a second end coupled to the ground, a third end coupled to the first node; and (D) resistor means coupled between the output node and the power supply for providing a positive potential at the output node when the third transistor is not conducting, wherein when the powers supply has not reached the predetermined level, the third transistor is not conducting and the output node outputs the reset signal that is the positive potential, wherein when the power supply rises above the predetermined level, the third transistor starts to conduct and the output node registers a ground potential and ceases to output the reset signal, wherein the first, second, and third transistors are of the same channel type such that the circuitry operates substantially independent of process variation and temperature variation.
Claim 11
Dependent Claim
22 words
The circuitry of claim 8, wherein each of the first, second, and third transistors has a threshold voltage of approximately one volt.
Claim 12
Dependent Claim
21 words
The circuitry of claim 9, wherein the threshold voltage of each of the first, second, and third transistors can be changed.
Claim 13
Dependent Claim
15 words
The circuitry of claim 8, wherein the first, second, and third transistors are N-channel transistors.
Claim 14
Dependent Claim
14 words
The circuitry of claim 8, further comprising an inverter coupled to the output node.
Claim 15
Dependent Claim
13 words
The circuitry of claim 8, wherein the resistor means comprises a diffusion resistor.
Claim 16
Dependent Claim
19 words
The circuitry of claim 8, wherein the predetermined level is in a range between 2 volts and 2.5 volts.
Claim 17
Dependent Claim
16 words
The nonvolatile memory of claim 8, wherein the nonvolatile memory is electrically programmable and electrically erasable.
Claim 18
Dependent Claim
352 words
A computer system, comprising: (A) a system bus; (B) a central processing unit (CPU) coupled to the system bus; (C) a plurality of peripheral devices, each of which being coupled to the system bus; (D) a nonvolatile memory coupled to system bus, wherein the nonvolatile memory further comprises (i) a memory array; (ii) a control circuitry coupled to the memory array for controlling operations of the memory array; and (iii) a detection circuit coupled to the control circuitry and coupled to receive a power supply for detecting potential level of the power supply and for generating a reset signal to reset the control circuitry until the potential level of the power supply rises above a predetermined voltage, wherein the detection circuit further comprises (1) a first transistor having a first end coupled to receive the power supply, a second end coupled to a first node, and a third end coupled to the first node; (2) a second transistor having a first end coupled to the first node, a second end couple to ground, and a third end coupled to the ground, wherein the first and second transistors function as a voltage divider; (3) a third transistor having a first end coupled to the power supply, a second end coupled to an output node, a third end coupled to the first node; and (4) resistor means coupled between the output node and the ground for coupling the output node to the ground when the third transistor is not conducting, and for providing a positive potential at the output node when the third transistor is conducting, wherein when the power supply does not reach the predetermined voltage level, the third transistor is not conducting and the output node outputs the reset signal that is a ground potential, wherein when the power supply rises above the predetermined voltage level, the third transistor starts to conduct and the output node registers the positive potential and ceases to output the reset signal, wherein the first, second, and third transistor are of the same channel type such that the circuitry operates independent of process variation and temperature variation.
Claim 19
Dependent Claim
352 words
A computer system, comprising: (A) a system bus; (B) a central processing unit (CPU) coupled to the system bus; (C) a plurality of peripheral devices, each of which being coupled to the system bus; (D) a nonvolatile memory coupled to system bus, wherein the nonvolatile memory further comprises (i) a memory array; (ii) a control circuitry coupled to the memory array for controlling operations of the memory array; and (iii) a detection circuit coupled to the control circuitry and coupled to receive a power supply for detecting potential level of the power supply and for generating a reset signal to reset the control circuitry until the potential level of the power supply rises above a predetermined voltage, wherein the detection circuit further comprises (1) a first transistor having a first end coupled to receive the power supply, a second end coupled to a first node, and a third end coupled to the first node; (2) a second transistor having a first end coupled to the first node, a second end couple to ground, and a third end coupled to the ground, wherein the first and second transistors function as a voltage divider; (3) a third transistor having a first end coupled to the power supply, a second end coupled to an output node, a third end coupled to the first node; and (4) resistor means coupled between the output node and the ground for coupling the output node to the ground when the third transistor is not conducting, and for providing a positive potential at the output node when the third transistor is conducting, wherein when the power supply does not reach the predetermined voltage level, the third transistor is not conducting and the output node outputs the reset signal that is a ground potential, wherein when the power supply rises above the predetermined voltage level, the third transistor starts to conduct and the output node registers the positive potential and ceases to output the reset signal, wherein the first, second, and third transistor are of the same channel type such that the circuitry operates independent of process variation and temperature variation.
Claim 20
Dependent Claim
23 words
The computer system of claim 16, wherein each of the first, second, and third transistors has a threshold voltage of approximately one volt.
Claim 21
Dependent Claim
16 words
The computer system of claim 16, wherein the first, second, and third transistors are P-channel transistors.
Claim 22
Dependent Claim
24 words
The computer system of claim 16, wherein the predetermined voltage level can be changed by changing size ratio of the first and second transistors.
Claim 23
Dependent Claim
14 words
The computer system of claim 16, wherein the resistor means comprises a diffusion resistor.
Claim 24
Dependent Claim
21 words
The computer system of claim 16, wherein the predetermined voltage level is in a range between 2 volts and 2.5 volts.
Claim 25
Dependent Claim
16 words
The computer system of claim 16, wherein the nonvolatile memory is electrically programmable and electrically erasable.
References Cited (Backward Citations)
US4975883A
Cited
US5119163A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-04 | 1997-10-04 | 1998-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-04 | 2001-10-04 | 2002-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-04 | 2005-10-04 | 2006-04-05 | $7700.00 | Window Closed / Lapsed |