Interconnect system initiating data transfer over launch bus at source's clock speed and transfering data over data path at receiver's clock speed

Claim 2

In a computer system having a first component and a second component, a computer interconnect for transferring packets of data between the first and second components, the computer interconnect comprising: a first launch bus; a first node coupled to the first component; a second node coupled to the second component, wherein the first node includes: a first buffer coupled to the first component for storing a first data packet received from the first component; a first router coupled to the first launch bus and the first component, the first router for storing a first header associated with the first data packet, the first router for transferring the first header to the second node via the first launch bus at a first clock speed of the first component, the first header indicating that the first data packet exists for transfer to the second node; a first data path coupled to the first buffer and the second node for transferring the first data packet from the first buffer to the second node at a second clock speed of the second component.

Claim 3

In a computer system having a first component and a second component, a computer interconnect for transferring packets of data between the first and second components, the computer interconnect comprising:. a first launch bus; a first node coupled to the first component; a second node coupled to the second component, wherein the first node includes: a first buffer coupled to the first component for storing a first data packet received from the first component; a first router coupled to the first launch bus and the first component, the first router for storing a first header associated with the first data packet, the first router for transferring the first header to the second node at a first clock speed of the first component, the first header indicating that the first data packet exists for transfer to the second component; a first data path coupled to the first buffer and the Second component for transferring the first data packet from the first buffer to the second component at a second clock speed of the second component, and wherein the second node comprises: a second router coupled to the launch bus and the second component, the second router for storing the first header; and a first reply bus coupled to the first router and the second router for transferring a first signal from the second router to the first router, the first signal indicating that transfer of the first data packet from the first buffer to the second component is complete.

Claim 4

In a computer system having a first component and a second component, a computer interconnect for transferring packets of data between the first and second components, the computer interconnect comprising:. a first launch bus; a first node coupled to the first component; a second node coupled to the second component, wherein the first node includes: a first buffer coupled to the first component for storing a first data packet received from the first component; a first router coupled to the first launch bus and the first component, the first router for storing a first header associated with the first data packet, the first router for transferring the first header to the second node at a first clock speed of the first component, the first header indicating that the first data packet exists for transfer to the second component; a first data path coupled to the first buffer and the Second component for transferring the first data packet from the first buffer to the second component at a second clock speed of the second component, and wherein the second node comprises: a second router coupled to the launch bus and the second component, the second router for storing the first header; and a first reply bus coupled to the first router and the second router for transferring a first signal from the second router to the first router, the first signal indicating that transfer of the first data packet from the first buffer to the second component is complete.

Claim 5

The computer interconnect of claim 2, wherein the second router comprises: a first circuit coupled to the first launch bus for receiving the first header and for determining whether the second node can accept data from the first node; a destination header buffer for storing the first header if the first circuit determines that the second node can accept data from the first node.

Claim 6

The computer interconnect of claim 2, wherein the first header includes: destination information describing the second component as a destination of the first data packet; arbitration information describing a type of arbitration to be used; priority information describing priority of the first data packet; operation information describing a type of operation; and amount information describing an amount of data in the first data packet to be transferred.

Claim 7

The computer interconnect of claim 2, wherein the second node further comprises: a second buffer coupled to the second component for storing a second data packet received from the second component; and a second data path coupled to the second buffer and the first component for transferring the second data packet from the second buffer to the first component at the first clock speed, wherein the second router is for storing a second header associated with the second data packet, the second router for transferring the second header to the first node at the second clock speed, the second header indicating that the second data packet exists for transfer to the first component.

Claim 8

The computer interconnect of claim 5, wherein the first node transmits the first data packet to the second component simultaneously with transmission of the second data packet from the second node to the first component.

Claim 9

The computer interconnect of claim 5, wherein the first data path and the second data path uni-directional.

Claim 10

A computer system comprising: a first component; a second component; a primary computer interconnect coupled to the first and second components; and a complementary computer interconnect coupled to the first and second components comprising: a first launch bus; a first node coupled to the first component; a second node coupled to the second component, wherein the first node includes: a first buffer coupled to the first component for storing a first data packet received from the first component; a first router coupled to the first launch bus and the first component, the first router for storing a first header associated with the first data packet, the first router for transferring the first header to the second node at a first clock speed of the first component, the first header indicating that the first data packet exists for transfer to the second component; a first data path coupled to the first buffer and the second component for transferring the first data packet from the first buffer to the second component at a second clock speed of the second component.

Claim 11

A computer system comprising: a first component; a second component; a primary computer interconnect coupled to the first and second components; and a complementary computer interconnect coupled to the first and second components comprising: a first launch bus; a first node coupled to the first component; a second node coupled to the second component, wherein the first node includes: a first buffer coupled to the first component for storing a first data packet received from the first component; a first router coupled to the first launch bus and the first component, the first router for storing a first header associated with the first data packet, the first router for transferring the first header to the second node at a first clock speed of the first component, the first header indicating that the first data packet exists for transfer to the second component; a first data path coupled to the first buffer and the second component for transferring the first data packet from the first buffer to the second component at a second clock speed of the second component.

Claim 12

In a computer system having a first component and a second component, a computer interconnect for transferring data between the first and second components, the computer interconnect comprising: a first launch bus; a first node coupled to the first component; a second node coupled to the second component, wherein the first node includes: a first interface circuit coupled to the first component for transferring signals between the first component and the first node; a first buffer coupled to the first interface circuit for storing data received from the first component; a first router coupled to the first launch bus and the first interface circuit, the first router for signaling to the second node at a first clock speed of the first component that data exists for transfer to the second component; a first data path coupled to the first buffer and the second node for transferring data from the first buffer to the second node at a second clock speed of the second component; the second node includes: a second interface circuit coupled to the second component for transferring signals between the second component and the second node; a second buffer coupled to the second interface circuit for storing data received from the second component; a second router coupled to the first launch bus and the second interface circuit, the second router for signaling to the first node at the second clock speed of the second component that data exists for transfer to the first component; and a second data path coupled to the second buffer for transferring data from the second buffer to the first node at the first clock speed of the first component.

Claim 13

In a computer system having a first component and a second component, a computer interconnect for transferring data between the first and second components, the computer interconnect comprising: a first launch bus; a first node coupled to the first component; a second node coupled to the second component, wherein the first node includes: a first interface circuit coupled to the first component for transferring signals between the first component and the first node; a first buffer coupled to the first interface circuit for storing data received from the first component; a first router coupled to the first launch bus and the first interface circuit, the first router for signaling to the second node at a first clock speed of the first component that data exists for transfer to the second component; a first data path coupled to the first buffer and the second node for transferring data from the first buffer to the second node at a second clock speed of the second component; the second node includes: a second interface circuit coupled to the second component for transferring signals between the second component and the second node; a second buffer coupled to the second interface circuit for storing data received from the second component; a second router coupled to the first launch bus and the second interface circuit, the second router for signaling to the first node at the second clock speed of the second component that data exists for transfer to the first component; and a second data path coupled to the second buffer for transferring data from the second buffer to the first node at the first clock speed of the first component.

Claim 14

The computer interconnect of claim 9, wherein the first node further includes: a first reply bus coupled to the first router and the second router for transferring a first signal from the second router to the first router, the first signal indicating that data transfer from the first buffer to the second component is complete.

Claim 15

The computer interconnect of claim 10, wherein the first interface circuit includes: a first translation channel for translating data in a first format received from the first component to a second format; a second translation channel for translating data in the second format to the first format for transfer to the first component.

Claim 16

The computer interconnect of claim 11, wherein the first format is one of a plurality of formats.

Claim 17

The computer interconnect of claim 12, wherein the plurality of formats include at least one format in which addresses and data are multiplexed and at least one format in which addresses and data appear separately.

Claim 18

The computer interconnect of claim 13 wherein the second format is an internal format of the computer interconnect.

Claim 19

The computer interconnect of claim 9 wherein the first buffer comprises a plurality of first data buffers for storing packets of data received from the first component.

Claim 20

The computer interconnect of claim 15, wherein at least one of the plurality of data buffers is reserved for read response operations.

Claim 21

The computer interconnect of claim 15, wherein the first buffer further comprises a plurality of first address buffers, each of the plurality of first address buffers for storing an address associated with data stored in a corresponding one of the plurality of first data buffers.

Claim 22

The computer interconnect of claim 17, wherein the first router is for sending a first header to the second node via the first launch bus to indicate that a first data packet stored in a selected one of the plurality of first data buffers is to be transferred to the second node.

Claim 23

The computer interconnect of claim 18, wherein the first header includes: destination information describing the second component as a destination of the first data packet; arbitration information describing the type of arbitration to be used; priority information describing priority of the first data packet; operation information describing a type of operation; and amount information describing an amount of data in the first data packet to be transferred.

Claim 24

The computer interconnect of claim 19, wherein the second router comprises: a first circuit coupled to the first launch bus for receiving the header and for determining whether the second node can accept data from the first node; a destination header buffer for storing the first header if the first circuit determines that the second node can accept data from the first node.

Claim 25

The computer interconnect of claim 20, wherein the second buffer comprises a plurality of second data buffers and a plurality of second address buffers, each of the plurality of second address buffers for storing an address associated with data stored in a corresponding one of the plurality of second data buffers.

Claim 26

The computer interconnect of claim 21, wherein said destination header buffer comprises a first destination header buffer which stores the first header and a second destination header buffer which stores a second header, the second header indicating a second data packet, the second router further comprising: priority arbitration circuit for selecting either the first data packet or the second data packet to be transferred to the second node in response to the first header and the second header.

Claim 27

The computer interconnect of claim 22 wherein the priority arbitration circuit selects the first data packet for transfer if a priority of the first data packet is a highest priority.

Claim 28

The computer interconnect of claim 23, wherein the priority arbitration selects either the first data packet or the second data packet for transfer on a round robin basis if the first and second data packets are of equal priority.

Claim 29

The computer interconnect of claim 22, wherein the priority arbitration circuit selectively promotes the priority of the first data packet.

Claim 30

The computer interconnect of claim 25, wherein the second router transmits the first signal via the reply bus in response to a transfer of the first data packet being complete.

Claim 31

The computer interconnect of claim 26, wherein the first data path and the second data path are uni-directional.

Claim 32

The computer interconnect of claim 27, wherein the first node is capable of transferring data to the second node while simultaneously receiving data from the second node.

Claim 33

The computer interconnect of claim 28, wherein the computer includes a system bus as a primary computer interconnect such that the computer interconnect is a complementary interconnect.

Claim 34

The computer interconnect of claim 9, wherein the first and second components are a processor and a memory, respectively.

Claim 35

The computer interconnect of claim 30, wherein the memory is a frame buffer memory.

Claim 36

The computer interconnect of claim 30, wherein the memory is a random access memory.

Claim 37

The computer interconnect of claim 9, wherein the first and second components are both processors.

Claim 38

The computer interconnect of claim 9, wherein the first and second components are a first memory and a second memory, respectively.

Claim 39

The computer interconnect of claim 9, wherein the first and second components are a processor and a first peripheral component, respectively.

Claim 40

The computer interconnect of claim 9, wherein the first and second components are both peripheral components.

Claim 41

The computer interconnect of claim 9, wherein the first and second components are a memory and a peripheral component, respectively.

Claim 42

The computer interconnect of claim 9, wherein the first data path and the second data path are uni-directional.

Claim 43

The computer interconnect of claim 9, wherein the first node is capable of transferring data to the second node while simultaneously receiving data from the second node.

Claim 44

The computer interconnect of claim 39, wherein a system bus is a primary computer interconnect for the computer and the computer interconnect is a complementary interconnect.

Claim 45

In a computer system having a first component, a second component, and a third component, wherein each of the first, second and third components are components which are typically joined to a system bus, a computer interconnect for transferring a plurality of packets of data simultaneously between individual ones of the first, second and third components, the computer interconnect comprising: a first launch bus; a first node coupled to the first component; a second node coupled to the second component; a third node coupled to the third component, wherein the first node includes: a first interface circuit coupled to the first component for transferring signals between the first component and the first node; a first buffer coupled to the first interface circuit for storing data received from the first component; a first router coupled to the first launch bus and the first interface circuit, the first router for signaling to the second node at a first clock speed of the first component that data exists for transfer to the second component, and for signaling to the third node at the first clock speed that data exists for transfer to the third component; a first data path coupled to the first buffer and the second node for transferring data from the first buffer to the second node at a second clock speed of the second component; a second data path coupled to the first buffer and the third node for transferring data from the first buffer to the third node at a third clock speed of the third component; the second node includes: a second interface circuit coupled to the second component for transferring signals between the second component and the second node; a second buffer coupled to the second interface circuit for storing data received from the second component; a second router coupled to the first launch bus and the second interface circuit, the second router for signaling to the first node at the second clock speed that data exists for transfer to the first component, and for signaling to the third node at the second clock speed that data exists for transfer to the third component; a third data path coupled to the second buffer and the first node for transferring data from the second buffer to the first node at the first clock speed; a fourth data path coupled to the second buffer and the third node for transferring data from the second buffer to the third node at the third clock speed; the third node includes: a third interface circuit coupled to the third component for transferring signals between the third component and the third node; a third buffer coupled to the third interface circuit for storing data received from the third component; a third router coupled to the first launch bus and the third interface circuit, the third router for signaling to the first node at the third clock speed that data exists for transfer to the first component; and for signaling to the second node at the third clock speed that data exists for transfer to the second component; a fifth data path coupled to the third buffer and the first node for transferring data from the third buffer to the first node at the first clock speed; a sixth data path coupled to the third buffer and the second node for transferring data from the third buffer to the second node at the third clock speed.

Claim 46

In a computer system having a first component, a second component, and a third component, wherein each of the first, second and third components are components which are typically joined to a system bus, a computer interconnect for transferring a plurality of packets of data simultaneously between individual ones of the first, second and third components, the computer interconnect comprising: a first launch bus; a first node coupled to the first component; a second node coupled to the second component; a third node coupled to the third component, wherein the first node includes: a first interface circuit coupled to the first component for transferring signals between the first component and the first node; a first buffer coupled to the first interface circuit for storing data received from the first component; a first router coupled to the first launch bus and the first interface circuit, the first router for signaling to the second node at a first clock speed of the first component that data exists for transfer to the second component, and for signaling to the third node at the first clock speed that data exists for transfer to the third component; a first data path coupled to the first buffer and the second node for transferring data from the first buffer to the second node at a second clock speed of the second component; a second data path coupled to the first buffer and the third node for transferring data from the first buffer to the third node at a third clock speed of the third component; the second node includes: a second interface circuit coupled to the second component for transferring signals between the second component and the second node; a second buffer coupled to the second interface circuit for storing data received from the second component; a second router coupled to the first launch bus and the second interface circuit, the second router for signaling to the first node at the second clock speed that data exists for transfer to the first component, and for signaling to the third node at the second clock speed that data exists for transfer to the third component; a third data path coupled to the second buffer and the first node for transferring data from the second buffer to the first node at the first clock speed; a fourth data path coupled to the second buffer and the third node for transferring data from the second buffer to the third node at the third clock speed; the third node includes: a third interface circuit coupled to the third component for transferring signals between the third component and the third node; a third buffer coupled to the third interface circuit for storing data received from the third component; a third router coupled to the first launch bus and the third interface circuit, the third router for signaling to the first node at the third clock speed that data exists for transfer to the first component; and for signaling to the second node at the third clock speed that data exists for transfer to the second component; a fifth data path coupled to the third buffer and the first node for transferring data from the third buffer to the first node at the first clock speed; a sixth data path coupled to the third buffer and the second node for transferring data from the third buffer to the second node at the third clock speed.

Claim 47

The computer interconnect of claim 41, wherein the first node further includes: a first reply bus coupled to the first router and the second router for transferring a first signal from the second router to the first router, the first signal indicating that data transfer from the first buffer to the second component is complete; a second reply bus coupled to the first router and the third router for transferring a second signal from the third router to the first router, the second signal indicating that data transfer from the first buffer to the third component is complete.

Claim 48

The computer interconnect of claim 42, wherein the first interface circuit includes: a first translation channel for translating data in a first format received from the first component to a second format; a second translation channel for translating data in the second format to the first format for transfer to the first component.

Claim 49

The computer interconnect of claim 43, wherein the first format is one of a plurality of formats.

Claim 50

The computer interconnect of claim 44, wherein the plurality of formats include at least one format in which addresses and data are multiplexed and at least one format in which addresses and data appear separately.

Claim 51

The computer interconnect of claim 45 wherein the second format is an internal format of the computer interconnect.

Claim 52

The computer interconnect of claim 41 wherein the first buffer comprises a plurality of first data buffers for storing packets of data received from the first component.

Claim 53

The computer interconnect of claim 47, wherein at least one of the plurality of data buffers is reserved for read response operations.

Claim 54

The computer interconnect of claim 47, wherein the first buffer further comprises a plurality of first address buffers, each of the plurality of first address buffers for storing an address associated with data stored in a corresponding one of the plurality of first data buffers.

Claim 55

The computer interconnect of claim 49, wherein the first router is for sending a first header to the second node via the first launch bus to indicate that a first data packet stored in a selected one of the plurality of data buffers is to be transferred to the second node, and for sending a second header to the third node via the first launch bus to indicate that a second data packet stored in a selected one of the plurality of first data buffers is to be transferred to the third node.

Claim 56

The computer interconnect of claim 50, wherein the first header includes: destination information describing the second component as a destination of the first data packet; arbitration information describing the type of arbitration to be used; priority information describing priority of the first data packet; operation information describing a type of operation; and amount information describing an amount of data in said first data packet to be transferred.

Claim 57

The computer interconnect of claim 51, wherein the second router comprises: a first circuit coupled to the first launch bus for receiving the first header and for determining whether the second node can accept data from the first node; a plurality of destination header buffers, each of the plurality of destination header buffers for storing the first header if the first circuit determines that the second node can accept data from the first node.

Claim 58

The computer interconnect of claim 52, wherein the second buffer comprises a plurality of second data buffers and a plurality of second address buffers, each of the plurality of second address buffers for storing an address associated with data stored in a corresponding one of the plurality of second data buffers.

Claim 59

The computer interconnect of claim 53, wherein a first destination header buffer stores the first header and a second destination header buffer stores a third header, the third header indicating a third data packet received from the third node via the first launch bus, the second router further comprising: priority arbitration circuit for selecting either the first data packet or the third data packet to be transferred to the second node in response to the first header and the third header.

Claim 60

The computer interconnect of claim 54 wherein the priority arbitration circuit selects the first data packet for transfer if a priority of the first data packet is a highest priority.

Claim 61

The computer interconnect of claim 54, wherein the priority arbitration selects either the first data packet or the third data packet for transfer on a round robin basis if the first and third data packets are of equal priority.

Claim 62

The computer interconnect of claim 56, wherein the priority arbitration circuit selectively promotes the priority of the first data packet.

Claim 63

The computer interconnect of claim 57, wherein the second router transmits the first signal via the reply bus in response to a transfer of the first data packet being complete.

Claim 64

The computer interconnect of claim 58, wherein the first data path and the second data path are uni-directional.

Claim 65

The computer interconnect of claim 59, wherein the first node is capable of transferring data to the second node while simultaneously receiving data from the second node.

Claim 66

The computer interconnect of claim 60, wherein the computer includes a system bus as a primary computer interconnect such that the computer interconnect is a complementary interconnect.

Claim 67

The computer interconnect of claim 41, wherein the first and second components are a processor and a memory, respectively.

Claim 68

The computer interconnect of claim 62, wherein the memory is a frame buffer memory.

Claim 69

The computer interconnect of claim 62, wherein the memory is a random access memory.

Claim 70

The computer interconnect of claim 41, wherein the first and second components are both processors.

Claim 71

The computer interconnect of claim 41, wherein the first and second components are a first memory and a second memory, respectively.

Claim 72

The computer interconnect of claim 41, wherein the first and second components are a processor and a first peripheral component, respectively.

Claim 73

The computer interconnect of claim 41, wherein the first and second components are both peripheral components.

Claim 74

The computer interconnect of claim 41, wherein the first and second components are a memory and a peripheral component, respectively.

Claim 75

The computer interconnect of claim 41, wherein the first data path and the second data path are uni-directional.

Claim 76

The computer interconnect of claim 41, wherein the first node is capable of transferring data to the second node while simultaneously receiving data from the second node.

Claim 77

The computer interconnect of claim 41, wherein a system bus is a primary computer interconnect for the computer and the computer interconnect is a complementary interconnect.