US4939644A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input/output controller for controlling the sequencing of the execution of input/output commands in a data processing system
Assignee: EMC Corp
•
Filing: 1987-01-09
•
Granted: 1990-07-03
•
Expires: 2007-01-09
Abstract
Abstract A data processing system which includes a host processor and an input/output (I/O) controller unit for controlling communication with I/O devices. The I/O controller unit responds to a plurality of I/O commands from the host processor each of which is associated with one of a plurality of control block lists each containing one or more control commands. The I/O controller unit can access and store control commands from each of the plurality of control block lists and execute the stored commands from such lists in a selected order for providing the most effective execution thereof.
Inventors
- 👤 David M. Harrington
- 👤 Steve A. Caldara
- 👤 Louis A. Lemone
- 👤 Kenneth R. Andrews, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:20
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F13/126
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
278 words
A system for controlling input/output operations required by a host computer, which includes host processor means and host memory means, in communication with one or more input/output devices, said system comprising: an input/output controller unit connected to said host computer and to said one or more input/output devices for controlling said input/output operation in response to input/output commands from said host processor means, said controller unit including controller processor means and controller memory means; said host memory means being accessible to said controller unit for storing a plurality of control block lists, each control block list corresponding to one of said input/output commands and including control blocks of command information; means for transferring one or more input/output commands from said host processor means to said controller processor means of said controller unit; said controller processor means being responsive to said input/output commands transferred thereto for successively accessing from said host memory means the control block lists corresponding to said input/output commands; said controller memory means being connected to said controller processor means for storing said control block lists, each including command information, control information supplied by said host processor means, status return information supplied by said controller processor means, and error information concerning errors which arise during execution of the operation corresponding to said control block of command information; said controller processor means includes means for selecting one of plurality of different sequences of said control block of command information from said control block lists in accordance with a predetermined algorithm in said controller memory means; and means responsive to said selected sequence of control blocks of command information for executing the operations required by said input/output commands.
Claim 2
Independent Claim
278 words
A system for controlling input/output operations required by a host computer, which includes host processor means and host memory means, in communication with one or more input/output devices, said system comprising: an input/output controller unit connected to said host computer and to said one or more input/output devices for controlling said input/output operation in response to input/output commands from said host processor means, said controller unit including controller processor means and controller memory means; said host memory means being accessible to said controller unit for storing a plurality of control block lists, each control block list corresponding to one of said input/output commands and including control blocks of command information; means for transferring one or more input/output commands from said host processor means to said controller processor means of said controller unit; said controller processor means being responsive to said input/output commands transferred thereto for successively accessing from said host memory means the control block lists corresponding to said input/output commands; said controller memory means being connected to said controller processor means for storing said control block lists, each including command information, control information supplied by said host processor means, status return information supplied by said controller processor means, and error information concerning errors which arise during execution of the operation corresponding to said control block of command information; said controller processor means includes means for selecting one of plurality of different sequences of said control block of command information from said control block lists in accordance with a predetermined algorithm in said controller memory means; and means responsive to said selected sequence of control blocks of command information for executing the operations required by said input/output commands.
Claim 3
Dependent Claim
36 words
A system in accordance with claim 1 wherein said host computer further includes a host main memory, the memory means storing said one or more control block lists being a part of said host main memory.
Claim 4
Dependent Claim
45 words
A system in accordance with claim 2 and further including a high speed data channel for transferring information between said host main memory and said controller unit, said controller processor means accessing said one or more control block lists via said high speed data channel.
Claim 5
Dependent Claim
32 words
A system in accordance with claim 1 wherein said transferring means comprises bus means interconnecting said host processor means and said controller unit, said input/output commands being transferred via said bus means.
Claim 6
Dependent Claim
27 words
A system in accordance with claim 4 wherein said controller unit includes command storage means for storing the input/output said commands transferred from said host processor means.
References Cited (Backward Citations)
US3728693A
Cited
US4435752A
Cited
US4006466A
Cited
US4075691A
Cited
US4156932A
Cited
US4417304A
Cited
US4783739A
Cited
US4384324A
Cited
US4426679A
Cited
US4451884A
Cited
US4583165A
Cited
US4488258A
Cited
US4543626A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-02 | 1994-01-01 | 1994-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-02 | 1998-01-01 | 1998-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-02 | 2002-01-01 | 2002-07-03 | $7700.00 | Window Closed / Lapsed |