System for efficiently transferring data between a high speed channel and a low speed I/O device

Claim 1

In a data processing system having at least one peripheral data input/output device, and a data channel having a channel data transfer rate substantially greater than a data transfer rate of said peripheral input/output device, a data buffer interface comprising: a buffer memory for receiving data of a plurality of block lengths from said peripheral device, and transferring said data to said data channel; a threshold register for storing the identity of a data word within said data block which indicates the start of a transfer cycle for transferring data from said buffer memory to said data channel; a load control for loading each data word sequentially received from said peripheral device into said buffer memory; an unload control connected to unload each data word stored in said buffer memory at a rate determined by said data channel data transfer rate; a comparator means connected to enable said unload control when said load control loads a data word identified by said threshold register into said buffer memory, whereby data transfer to said channel is initiated before said buffer memory has completely filled; and a microprocessor connected to supply said threshold register with the identity of said data word which indicates the start of said transfer cycle, said microprocessor connected to receive a signal from said unload control for determining a new threshold identity for subsequent blocks of data based upon the length of a previous block of data transferred from said buffer memory to said channel.