Magnetic tape-data link processor providing automatic data transfer

Claim 2

A peripheral-controller for executing data transfer operations between a buffer memory means in said peripheral-controller and a main host computer or a magnetic tape peripheral unit, the peripheral-controller comprising: (a) a common front end circuit unit for sequencing micro-code instructions to effect data transfers of blocks of data between said buffer memory means and said host computer or said magnetic tape peripheral unit, said front end circuit unit being initiated by command from said host computer and including: (a1) buffer memory means for temporary storage of data-in-transit between said magnetic tape peripheral unit and said host computer, said buffer memory means organized into a plurality of n data storage blocks whereby each block stores a plurality of data words; (a2) instruction sequencing means providing control signals to a peripheral dependent circuit unit; (a3) means to receive block status information signals from a means for registering the number "n" of full data blocks residing in said buffer memory means; (a4) means for generating control signals for said peripheral dependent circuit unit, said means operating in response to receipt of said block status information signals; (b) said peripheral dependent circuit unit operating under control of said common front end circuit unit and functioning to control data transfers into and out of said buffer memory means to and from said host computer or said magnetic tape peripheral unit, said peripheral dependent circuit unit including: (b1) means to execute automatic read operations for transferring blocks of data from said magnetic tape peripheral unit to said buffer memory means; (b2) means to execute automatic write operations for transferring blocks of data from said buffer memory means to said magnetic tape peripheral unit; (b3) first means to transfer data from said host computer to said buffer memory means, and second means to transfer data from said buffer memory to said host computer, said first and second means to transfer including: (b3-1) burst mode transfer means for transferring one or more full blocks of data between said buffer memory means and said host computer with a single instruction from said common front end circuit unit; (b4) said means for registering a number "n" of full data blocks residing in said buffer memory means, and for providing a block status information signal to said common front end circuit unit, said means for registering including: (b4a) address register means for receiving address data to be used in accessing locations in said buffer memory means and for providing numerical data signals to a block counter logic unit wherein said numcrical data signals indicate the amount of data transferred into and the amount of data transferred out of said buffer memory means; (b4b) a block counter logic unit connected to receive said numerical data signals from said address register means and to provide first and second logic output signals to a gating means; (b4c) said gating for permitting said first and second logic output signals to operate a counter means, said first and second output signals operating to shift up or shift down the count in said counter means; (b4d) said counter means functioning to maintain a count of the number "n" of full data blocks residing in said buffer memory means.

Claim 3

The peripheral-controller of claim 1 wherein said means to execute automatic read operations, from said peripheral unit to said buffer memory means, operates concurrently with said second means to transfer data from said buffer memory means to said host computer, wherein the term "concurrently" signifies that, on any automatic Read/Write cycle, blocks of data words can be transferred between said buffer memory means and both of said host computer and said peripheral unit.

Claim 4

The peripheral-controller of claim 1 wherein said means to executre automatic write operations, from said buffer memory means to said peripheral unit, operates concurrently with said first means to transfer data from said main host computer to said buffer memory means, wherein the term "concurrently" signifies that, on any automatic Read/Write cycle, blocks of data words can be transferred between said buffer memory means and both of said host computer and said peripheral unit.

Claim 5

A peripheral-controller, designated as a data-link-processor, for managing data transfers between a main host computer and a magnetic tape peripheral unit, said peripheral-controller comprising: (a) a common front end circuit for sequencing micro-code instructions to execute data transfer between a buffer memory in said common front end circuit and said host computer or said magnetic tape peripheral unit, said front end circuit operating upon initiation of commands from said main host computer and providing control signals to a peripheral dependent circuit unit, said front end circuit including: (a1) a RAM buffer memory for temporarily Istoring data-in-transit between said magnetic tape peripheral unit and said main host comouter, said buffer memory being organized into a plurality of a memory block areas wherein each block area holds a plurality of data words; (a2) means to receive data block number status information, from a means to register, for selecting instructions for data transfer connections and operation in loading or unloading said buffer memory; (b) a peripheral-dependent circuit unit operating under control of said common front end circuit and functioning to control data transfers into said buffer memory from said main host computer or said magnetic tape peripheral unit, and functioning to control data transfers out of said buffer memory to said host computer or said magnetic tape peripheral unit, said peripheral dependent circuit unit including: (b1) means to register the number of full blocks of data residing in said buffer memory, said means to register including: (b1a) means to signal said common front end circuit with information data as to the presently existing number of blocks of data words residing in said buffer memory, said signal means including: (i) a block counter unit for registering the number of full blocks of data words residing in said buffer memory; (ii) a block counter logic unit, for raising or lowering the block count number in said block counter unit, and connected to receive first and second input signals respectively from a peripheral address register and a system address register; (iii) a peripheral address register connected to receive address data and providing said first input signal to said block counter logic unit to indicate the number of data words transferred between said magnetic tape peripheral unit and said buffer memory; (iv) a system address register connected to receive address data and providing said second input signal to said block counter logic unit to indicate the number of data words transferred between said main host computer and said buffer memory; (v) a control signal line from said common front end unit to said block counter logic unit for indicating a "Read" operation or a "Write" operation to regulate the increase or decrease of the block count number in said block counter unit; (b2) means to concurrently load data-in-transit into said buffer memory and to unload said data-in-transit out of said buffer memory, said data-in-transit being received from either of said main host computer or said magnetic tape peripheral unit and said data-in-transit being transmitted to either said magnetic tape peripheral unit or said main host computer; (b3) wherein said means to load and unload said buffer memory is controlled by the number "n" of data blocks conveyed by said means to signal to said common front end circuit, said common front end circuit selecting new microcode instructions dependent on the value of "n".

Claim 6

A peripheral-controller, designated as a data-link-processor, for managing data transfers between a main host computer and a magnetic tape peripheral unit, said peripheral-controller comprising: (a) a common front end circuit for sequencing micro-code instructions to execute data transfer between a buffer memory in said common front end circuit and said host computer or said magnetic tape peripheral unit, said front end circuit operating upon initiation of commands from said main host computer and providing control signals to a peripheral dependent circuit unit, said front end circuit including: (a1) a RAM buffer memory for temporarily Istoring data-in-transit between said magnetic tape peripheral unit and said main host comouter, said buffer memory being organized into a plurality of a memory block areas wherein each block area holds a plurality of data words; (a2) means to receive data block number status information, from a means to register, for selecting instructions for data transfer connections and operation in loading or unloading said buffer memory; (b) a peripheral-dependent circuit unit operating under control of said common front end circuit and functioning to control data transfers into said buffer memory from said main host computer or said magnetic tape peripheral unit, and functioning to control data transfers out of said buffer memory to said host computer or said magnetic tape peripheral unit, said peripheral dependent circuit unit including: (b1) means to register the number of full blocks of data residing in said buffer memory, said means to register including: (b1a) means to signal said common front end circuit with information data as to the presently existing number of blocks of data words residing in said buffer memory, said signal means including: (i) a block counter unit for registering the number of full blocks of data words residing in said buffer memory; (ii) a block counter logic unit, for raising or lowering the block count number in said block counter unit, and connected to receive first and second input signals respectively from a peripheral address register and a system address register; (iii) a peripheral address register connected to receive address data and providing said first input signal to said block counter logic unit to indicate the number of data words transferred between said magnetic tape peripheral unit and said buffer memory; (iv) a system address register connected to receive address data and providing said second input signal to said block counter logic unit to indicate the number of data words transferred between said main host computer and said buffer memory; (v) a control signal line from said common front end unit to said block counter logic unit for indicating a "Read" operation or a "Write" operation to regulate the increase or decrease of the block count number in said block counter unit; (b2) means to concurrently load data-in-transit into said buffer memory and to unload said data-in-transit out of said buffer memory, said data-in-transit being received from either of said main host computer or said magnetic tape peripheral unit and said data-in-transit being transmitted to either said magnetic tape peripheral unit or said main host computer; (b3) wherein said means to load and unload said buffer memory is controlled by the number "n" of data blocks conveyed by said means to signal to said common front end circuit, said common front end circuit selecting new microcode instructions dependent on the value of "n".