Peripheral dependent circuit for peripheral controller

Claim 2

A peripheral dependent circuit board, which when combined with a common control circuit card having a RAM buffer storage memory, forms a peripheral-controller operating to control data transfers between a host computer system and a peripheral terminal unit, said peripheral dependent circuit board comprising: (a) bi-directional data path means to said peripheral terminal unit; (b) address logic means for formulating addresses for the reading out and writing in of data in said RAM buffer storage memory; (c) multiplexor means for selecting a source of data that is to be transmitted to said RAM buffer storage memory; (d) error detection means for checking messages sent between said peripheral-controller and said host system and for checking messages between said peripheral controller and said peripheral terminal unit; (e) means to set a unique address to identify said peripheral-controller; (f) word-generation shift register means to provide control and information data to said peripheral teminal unit and/or said host computer system; (g) logic means for executing micro-code word operators received from said common control circuit card.

Claim 3

The peripheral dependent circuit board of claim 1 which includes: (i) receive register means for accepting data words from said host computer system or said peripheral terminal unit; (ii) transmit register means for temporily storing and transmitting data to said peripheral terminal unit; (iii) system address register means for accessing RAM buffer memory data for said host computer system; (iv) queue address register means for addressing specially dedicated areas of said RAM buffer storage memory; (v) peripheral address register means for accessing data in said RAM buffer storage memory for said peripheral terminal unit.

Claim 4

The peripheral dependent circuit board of claim 2 wherein said multiplexor means for selecting a source of data for said RAM buffer storage memory includes: means to select data from: said receive register means, said shift register means, or from the output of said RAM buffer storage memory.

Claim 5

The peripheral dependent circuit board of claim 2 wherein said address logic means for formulating addresses to said RAM buffer storage memory includes: (b1) selection means, using micro-code word signals from said common control circuit card, for selecting an address from either: said system address register means, said peripheral address register means, or said queue address register means.

Claim 6

The peripheral dependent circuit board of claim 4 which includes: comparator means for comparing the amount of data accessed by the said system address register with the amount of data accessed by the said peripheral address register to equally balance the amount of data written into the RAM buffer storage memory from the host computer with the amount of data read out of the RAM buffer memory transmitted to said peripheral terminal unit.

Claim 7

The peripheral dependent board of claim 4 which includes: comparator means for comparing the amount of data accessed by said peripheral address register means with the amount of data accessed by said system register means to equally balance the amount of data written into said RAM buffer memory from said peripheral terminal with the amount of data read out of the RAM buffer memory transmitted to said host computer system.

Claim 8

A peripheral dependent circuit board, which when combined with a common control circuit board having a RAM buffer memory, forms a peripheral-controller in a system wherein input/output descriptor commands and a data-linkword task identifier are tansmitted by a host computer to said peripheral-controller for execution of data transfer operations between a peripheral terminal and said host computer, and said peripheral-controller returns result descriptor words to said host computer to signal completion/ incompletion of the data transfer operation, said peripheral dependent circuit board comprising: (a) logic means to execute micro-code word operators from received said common control circuit board; (b) address logic means to transmit addresses for the reading out and writing in of data in said RAM buffer memory; (c) multiplexor means to select as a data source, for said RAM buffer memory, the peripheral terminal or said host computer; (d) word generation means to provide control data and information to said host computer and/or said peripheral terminal; (e) device data register means to buffer data received from or transmitted to said peripheral terminal; (f) device register control means to regulate data transfers between said peripheral terminal and said peripheral dependent circuit board; (g) data bus and control line means between said host computer and said peripheral dependent board.

Claim 9

A peripheral dependent circuit board, which when combined with a common control circuit board having a RAM buffer memory, forms a peripheral-controller in a system wherein input/output descriptor commands and a data-linkword task identifier are tansmitted by a host computer to said peripheral-controller for execution of data transfer operations between a peripheral terminal and said host computer, and said peripheral-controller returns result descriptor words to said host computer to signal completion/ incompletion of the data transfer operation, said peripheral dependent circuit board comprising: (a) logic means to execute micro-code word operators from received said common control circuit board; (b) address logic means to transmit addresses for the reading out and writing in of data in said RAM buffer memory; (c) multiplexor means to select as a data source, for said RAM buffer memory, the peripheral terminal or said host computer; (d) word generation means to provide control data and information to said host computer and/or said peripheral terminal; (e) device data register means to buffer data received from or transmitted to said peripheral terminal; (f) device register control means to regulate data transfers between said peripheral terminal and said peripheral dependent circuit board; (g) data bus and control line means between said host computer and said peripheral dependent board.

Claim 10

The peripheral dependent circuit board of claim 7 which includes: error detection means for checking message data transferred between said peripheral-controller and said peripheral terminal or said host computer.

Claim 11

The peripheral dependent circuit board of claim 7 wherein said word generation means includes: means to generate an a said result descriptor word to signal said host computer of the completion or non-completion of an a said input/output descriptor command initiated by said host computer.

Claim 12

The peripheral dependent circuit board of claim 7 which includes: means to balance the amount of data written into said RAM buffer memory with the amount of data read out from said RAM buffer memory.