EP0127007A2
Expired / Lapsed
EP
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Data processing interface apparatus
Assignee: International Business Machines Corp
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Filing: 1984-05-03
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Granted: —
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Expires: 2004-05-03
Abstract
Abstract Input data words of variable data field width are interfaced to a fixed width data bus. The apparatus includes a circuit incorporating a modulo Nc down shifter for translating an Nf bit length input data word into an Nc bit length output data word for interfacing with an Nc bit length data bus and further including mask means for generating a mask when the Nf bit length is not an even multiple of the Nc bit length.
Inventors
- 👤 Frederick Hayes Dill
- 👤 Daniel Tajen Ling
- 👤 Richard Edward Matick
- 👤 Dennis Jay Mcbride
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 07:50
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009; G06F13/4018
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
145 words
Data processing interface apparatus for interfacing between different or variable width data fields or blocks, comprising a data field register for storing a variable width data field having a number of data bits N ff a data bus register for storing selected groups of N c data bits from said data field register, a data bus having a width of N c bits, and a data logic means connected between said data field register and said data bus register, said data logic means functioning for sequentially transferring groups of N c data bits of said N f data bits from said data field register into first N c bit positions of said data bus register for connection to said N c width data bus until all of said N f data bits have been transferred into said data bus in groups of N c .
Claim 2
Dependent Claim
145 words
Data processing interface apparatus for interfacing between different or variable width data fields or blocks, comprising a data field register for storing a variable width data field having a number of data bits N ff a data bus register for storing selected groups of N c data bits from said data field register, a data bus having a width of N c bits, and a data logic means connected between said data field register and said data bus register, said data logic means functioning for sequentially transferring groups of N c data bits of said N f data bits from said data field register into first N c bit positions of said data bus register for connection to said N c width data bus until all of said N f data bits have been transferred into said data bus in groups of N c .
Claim 3
Dependent Claim
17 words
Apparatus according to Claim 1 wherein said data logic means includes a modulo N down-shifter circuit. c
Claim 4
Dependent Claim
60 words
Apparatus according to Claim 1 wherein said number of data bits N f in said data field register is larger than said data bus width of N c bits, and wherein said data logic means sequentially transfers said N f bits from said data field register to said data bus register in a series of groups of N c bits.
Claim 5
Dependent Claim
54 words
Apparatus according to Claim 3 wherein said data logic means further includes mask generator means for providing mask bits for bit positions in the last series of said transferred N f bits when said last series of bits is less than N c resulting from N not being a multiple of N c .
Claim 6
Dependent Claim
78 words
Apparatus according to Claim 4 wherein said data logic means includes means for storing the value of N as a binary number n , a cycle c counter, a multiplexer-adder and a shift-select register, wherein said binary number n c and said output of said cycle counter are applied through said multiplexer- adder to said shift select register to select the shift distance of said modulo N down- shifter circuit c for successive cycles of said cycle counter.
Claim 7
Dependent Claim
135 words
Apparatus according to Claim 5 wherein said data logic means further includes means connected to said data field register for storing the value of N f as a binary number n ft means connected to said N c storage means for the converting of the binary number n c to a negative value, means for combining the binary number n f and the negative binary number n c with the output of said cycle counter to provide a value N; register means for storing the value N; means for determining when said N value is negative; adding means for adding the binary number n c to said N value in said N register means to provide a resulting value R s ; and a mask select register for storing said resulting value R . s
References Cited (Backward Citations)
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