US4683534A
Expired / Lapsed
US
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Method and apparatus for interfacing buses of different sizes
Assignee: Motorola Solutions Inc
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Filing: 1985-06-17
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Granted: 1987-07-28
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Expires: 2005-06-17
Abstract
Abstract In a data processing system having a first bus sized to accomodate 2 x units of data and a second bus sized to accomodate 2 y units of data, where x and y are positive integers and y is less than or equal to x, a method and apparatus for determining y from the x least significant bits of a control address, concatenated with a decode control bit, and then decoding the (x-y) most significant bits of the x control address bits to determine which of x data unit transceivers coupled between the first and second buses should be enabled.
Inventors
- 👤 Donald L. Tietjen
- 👤 Michael W. Cruess
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 13:57
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009; G06F13/4018
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
172 words
In a data processing system comprising first and second buses, wherein the second bus is a 2 x sub-multiple of the first bus, x being a predetermined positive integer, a circuit for interfacing the first bus to the second bus, comprising: a size decoder for receiving as a size control signal the (x-1) least significant bits of a control address and a decoder control signal, the size decoder providing a size select signal indicative of the number y of consecutive least significant bits of the size control signal which are equal to logic one (1); an address decoder for receiving the x least significant bits of the control address and the size select signal, the address decoder providing 2 2 enable signals indicative of the encoding of the (x-y) most significant bits of the x control address bits; and .sup. x sets of buffers, each set coupling a selected portion of the first bus to a respective portion of the second bus in response to a respective one of the enable signals.
Claim 2
Dependent Claim
172 words
In a data processing system comprising first and second buses, wherein the second bus is a 2 x sub-multiple of the first bus, x being a predetermined positive integer, a circuit for interfacing the first bus to the second bus, comprising: a size decoder for receiving as a size control signal the (x-1) least significant bits of a control address and a decoder control signal, the size decoder providing a size select signal indicative of the number y of consecutive least significant bits of the size control signal which are equal to logic one (1); an address decoder for receiving the x least significant bits of the control address and the size select signal, the address decoder providing 2 2 enable signals indicative of the encoding of the (x-y) most significant bits of the x control address bits; and .sup. x sets of buffers, each set coupling a selected portion of the first bus to a respective portion of the second bus in response to a respective one of the enable signals.
Claim 3
Dependent Claim
133 words
In a data processing system comprising first and second buses, wherein the second bus is a 2 x sub-multiple of the first bus, x being a predetermined positive integer, a method for interfacing the first bus to the second bus, comprising: receiving as a size control signal (x-1) least significant bits of a control address and a decode control signal; providing a size select signal indicative of the number y of consecutive least significant bits of the size control signal which are equal to logic one (1); providing 2 x enable signals indicative of the encoding of the (x-y) most significant bits of the x control address bits; and coupling a selected portion of the first bus to a respective portion of the second bus in response to each of the enable signals.
Claim 4
Dependent Claim
133 words
In a data processing system comprising first and second buses, wherein the second bus is a 2 x sub-multiple of the first bus, x being a predetermined positive integer, a method for interfacing the first bus to the second bus, comprising: receiving as a size control signal (x-1) least significant bits of a control address and a decode control signal; providing a size select signal indicative of the number y of consecutive least significant bits of the size control signal which are equal to logic one (1); providing 2 x enable signals indicative of the encoding of the (x-y) most significant bits of the x control address bits; and coupling a selected portion of the first bus to a respective portion of the second bus in response to each of the enable signals.
Claim 5
Dependent Claim
190 words
A circuit for interfacing a first data bus size to simultaneously accomodate 2 x units of data to a second data bus sized to accomodate 2 y units of data, where x and y are positive integers and y is less than or equal to x, the circuit comprising: size decode means for receiving as a size control signal the (x-1) least significant bits of a control address and a decode control signal, the size decoder providing a size select signal indicative of the number y of consecutive least significant bits of the size control signal which are equal to logic one (1); address decoder means, responsive to the size select signal, for receiving the x control address bits, the address decode means providing 2 x unit enable signals indicative of the encoding of the (x-y) most significant bits of the x control address bits; and .sup. x sets of buffers, each set responsive to a respective one of the unit enable signals, for coupling each unit of the first bus to a selected unit of the second bus in response to a respective one of the unit enable signals.
Claim 6
Dependent Claim
190 words
A circuit for interfacing a first data bus size to simultaneously accomodate 2 x units of data to a second data bus sized to accomodate 2 y units of data, where x and y are positive integers and y is less than or equal to x, the circuit comprising: size decode means for receiving as a size control signal the (x-1) least significant bits of a control address and a decode control signal, the size decoder providing a size select signal indicative of the number y of consecutive least significant bits of the size control signal which are equal to logic one (1); address decoder means, responsive to the size select signal, for receiving the x control address bits, the address decode means providing 2 x unit enable signals indicative of the encoding of the (x-y) most significant bits of the x control address bits; and .sup. x sets of buffers, each set responsive to a respective one of the unit enable signals, for coupling each unit of the first bus to a selected unit of the second bus in response to a respective one of the unit enable signals.
Claim 7
Independent Claim
146 words
A method for interfacing a first data bus sized to simultaneously accomodate 2 x units of data to a second data bus sized to accomodate 2 y units of data, where x and y are positive integers and y is less than or equal to x, comprising the steps of: receiving as a size control signal the (x-1) least significant bits of a control address and a decode control signal; providing a size select signal indicative of the number y of consecutive least significant bits of the size control signal which are equal to logic one (1); providing 2 x unit enable signals indicative of the encoding of the (x-y) most significant bits of the x control address bits; and coupling each unit of the first bus to a selected unit of the second bus in response to a respective one of the unit enable signals.
Claim 8
Independent Claim
146 words
A method for interfacing a first data bus sized to simultaneously accomodate 2 x units of data to a second data bus sized to accomodate 2 y units of data, where x and y are positive integers and y is less than or equal to x, comprising the steps of: receiving as a size control signal the (x-1) least significant bits of a control address and a decode control signal; providing a size select signal indicative of the number y of consecutive least significant bits of the size control signal which are equal to logic one (1); providing 2 x unit enable signals indicative of the encoding of the (x-y) most significant bits of the x control address bits; and coupling each unit of the first bus to a selected unit of the second bus in response to a respective one of the unit enable signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-27 | 1991-01-26 | 1991-07-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-27 | 1995-01-26 | 1995-07-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-27 | 1999-01-26 | 1999-07-28 | $7700.00 | Window Closed / Lapsed |