US5638534A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory controller which executes read and write commands out of order
Assignee: Accentus Medical PLC
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Filing: 1995-03-31
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Granted: 1997-06-10
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Expires: 2015-03-31
Abstract
Abstract A memory subsystem includes a posted write buffer for dynamic random access memories (DRAMs). The posted write buffer includes read around logic to enable read accesses to be processed in advance of posted writes. Data are transferred from the posted write buffer to the DRAMs on a general first-in/first out basis; however, in order to take advantage of page mode operation, posted writes having the same row address as a current memory access are given priority over other posted writes such that the posted writes may be written out of order. In addition, comparisons are made between addresses of incoming read accesses and addresses of posted writes in order to expedite the transfer of posted writes having the same row addresses to memory in order to service the incoming read accesses on a timely basis. An improved write access buffer permits posted writes to be transferred to the DRAMs out of order without losing track of the skipped posted writes.
Inventors
- 👤 L. Randall Mote, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 00:48
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/18; G06F12/00; G06F12/02; G06F12/0215
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
268 words
A memory controller which controls a dynamic random access memory (DRAM) system which receives a plurality of write access requests having respective addresses and associated data to be written to said DRAM system at said addresses, each of said write addresses having a row address portion and a column address portion, said memory controller comprising: a buffer having a plurality of locations which temporarily store said write addresses and associated data for each of said write access requests until said data can be written to said DRAM system, said stored addresses and data being maintained in said buffer in an order corresponding to an order in which said write access requests are received; and an access sequence control circuit which selects address and data associated with one of said plurality of write access requests as a next access to said DRAM system, said access sequence control circuit comprising: a comparator which compares said row address portion of each of said stored addresses with said row address portion of a current access and identifies write access requests having respective row address portions identical to said row address portion of said current access; and an access selector circuit responsive to said comparator which selects one of said identified write access requests as a next access to said DRAM system before selecting a non-identified write access request having a row address portion different from said row address portion of said current access, said selection of said one of said identified write access requests being made even if said non-identified write access request was made prior to said identified write access request.
Claim 2
Dependent Claim
268 words
A memory controller which controls a dynamic random access memory (DRAM) system which receives a plurality of write access requests having respective addresses and associated data to be written to said DRAM system at said addresses, each of said write addresses having a row address portion and a column address portion, said memory controller comprising: a buffer having a plurality of locations which temporarily store said write addresses and associated data for each of said write access requests until said data can be written to said DRAM system, said stored addresses and data being maintained in said buffer in an order corresponding to an order in which said write access requests are received; and an access sequence control circuit which selects address and data associated with one of said plurality of write access requests as a next access to said DRAM system, said access sequence control circuit comprising: a comparator which compares said row address portion of each of said stored addresses with said row address portion of a current access and identifies write access requests having respective row address portions identical to said row address portion of said current access; and an access selector circuit responsive to said comparator which selects one of said identified write access requests as a next access to said DRAM system before selecting a non-identified write access request having a row address portion different from said row address portion of said current access, said selection of said one of said identified write access requests being made even if said non-identified write access request was made prior to said identified write access request.
Claim 3
Dependent Claim
93 words
The memory controller as defined in claim 1, wherein: said memory controller receives a read access request having a read address, said read address having a row address portion and a column address portion; said comparator compares said row address portion of said read address and identifies whether said row address portion of said read address is directed to said row address portion of said current access; and said access selector circuit selects said read access request as a next access prior to selecting said non-identified write access request as a next access.
Claim 4
Dependent Claim
111 words
The memory controller as defined in claim 2, wherein: said comparator further comprises logic which compares at least a portion of said column address portion of said read address with a corresponding portion of said column address portions of said plurality of write addresses in said buffer; and said address selector circuit selects said read access request before any write access request when said row address portion of said read address is identical to said row address portion of said current access and said portion of said column address portion of said read address is different from said corresponding portions of said column address portions of said identified write access requests.
Claim 5
Independent Claim
284 words
A method for controlling access to a dynamic random access memory (DRAM) system having a plurality of memory storage locations, wherein said DRAM system is accessed by applying a row address to said DRAM system and then applying a column address to said DRAM system, said DRAM system providing access to a plurality of locations having the same row address by changing only the column address between accesses, said method comprising the steps of: storing an address and associated data for each of a plurality of write access requests in a buffer, each address of said plurality of access requests comprising a row address portion and a column address portion, each address and associated data stored in an order in which said memory controller receives said access requests; performing a first access to said DRAM system at a first row address and a first column address; comparing said first row address portion with said row address portion of each access request stored in said buffer; when at least one access request in said buffer has a row address portion identical to said row address portion of said first access, selecting as a second access to said DRAM system an earliest received access request of said at least one access request having a row address portion identical to said row address portion of said first access, said at least one access request having an identical row address portion being selected before earlier access requests having non-identical row address portions; and when no access request in said buffer has a row address portion identical to said row address portion of said first access, selecting an earliest received access request in said buffer as said second access.
Claim 6
Independent Claim
284 words
A method for controlling access to a dynamic random access memory (DRAM) system having a plurality of memory storage locations, wherein said DRAM system is accessed by applying a row address to said DRAM system and then applying a column address to said DRAM system, said DRAM system providing access to a plurality of locations having the same row address by changing only the column address between accesses, said method comprising the steps of: storing an address and associated data for each of a plurality of write access requests in a buffer, each address of said plurality of access requests comprising a row address portion and a column address portion, each address and associated data stored in an order in which said memory controller receives said access requests; performing a first access to said DRAM system at a first row address and a first column address; comparing said first row address portion with said row address portion of each access request stored in said buffer; when at least one access request in said buffer has a row address portion identical to said row address portion of said first access, selecting as a second access to said DRAM system an earliest received access request of said at least one access request having a row address portion identical to said row address portion of said first access, said at least one access request having an identical row address portion being selected before earlier access requests having non-identical row address portions; and when no access request in said buffer has a row address portion identical to said row address portion of said first access, selecting an earliest received access request in said buffer as said second access.
Claim 7
Dependent Claim
150 words
The method as defined in claim 4, further comprising the steps of: comparing a row address portion and at least one bit of a column address portion of a read access request to row address portions and a corresponding bit of column address portions of said plurality of write access requests in said buffer; and when said row address portion of said read access is identical to a row address portion of at least one of said write access requests: performing said read access prior to said write accesses having an identical row address portion when said corresponding bits of said column address portions are different; and performing a write access prior to said read access when said at least one bit of said column address portion of said read access is identical to said at least one bit of said column address portion of one of said write accesses.
Claim 8
Independent Claim
141 words
A method of selecting a next access in a dynamic random access memory (DRAM) system having posted write requests to said DRAM system, wherein at least one of said posted writes has an address directed to a storage location having a row address identical to a row address of a current access to said DRAM system and at least one of said posted writes has an address directed to a storage location having a row address different from said row address of said current access, said method comprising the steps of: selecting an earliest received write access having an identical row address as a next access, prior to selecting any write access having a different row address; and when no write access has an identical row address, selecting an earliest write access having a different row address as a next access.
Claim 9
Independent Claim
141 words
A method of selecting a next access in a dynamic random access memory (DRAM) system having posted write requests to said DRAM system, wherein at least one of said posted writes has an address directed to a storage location having a row address identical to a row address of a current access to said DRAM system and at least one of said posted writes has an address directed to a storage location having a row address different from said row address of said current access, said method comprising the steps of: selecting an earliest received write access having an identical row address as a next access, prior to selecting any write access having a different row address; and when no write access has an identical row address, selecting an earliest write access having a different row address as a next access.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-09 | 2000-12-09 | 2001-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-09 | 2004-12-09 | 2005-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-09 | 2008-12-09 | 2009-06-10 | $7700.00 | Window Closed / Lapsed |