Method and apparatus for sharing data between processors in a computer system

Claim 2

A computer system comprising: a plurality of processors having at least one processor pair, each one of the plurality of processors including a write-back cache for temporary storage of copies of preselected data blocks, the plurality of processors being coupled to each other by a bus; a plurality of selectively setable identifiers, each one of the plurality of selectively setable identifiers associated with a respective copy of the preselected data blocks stored in the write-back caches of the plurality of processors; each one of the plurality of selectively setable identifiers being selectively set to indicate an incomplete state of the copy of the preselected data blocks associated with said one of the plurality of selectively setable identifiers; a first processor of a processor pair of the plurality of processors transmits a read request on the bus when the first processor preselects a particular data block for temporarily storing a copy thereof in the write back cache of the first processor; and a second processor of the processor pair of the plurality of processors transmits a preselected portion of the particular data block requested by the first processor on the bus when the particular data block is stored in the write-back cache of the second processor in an owned state, thereby giving partial ownership of the portion of the particular data block to the first processor, and said second processor sets the one of the plurality of selectively setable identifiers associated with the particular data block to indicate the incomplete state of the particular data block.

Claim 3

The computer system according to claim 1 wherein the first processor further comprises a write buffer for temporary storage of the portion of the particular data block transmitted by the second processor after the portion of the particular data block has been modified by the first processor.

Claim 4

The computer system according to claim 1 wherein the first and second processors are coupled by a second bus and wherein the second processor further comprises a write buffer for temporary storage of the portion of the particular data block after the portion of the particular data block has been modified by the first processor and transmitted by the first processor across the second bus to the second processor.

Claim 5

The computer system of claim 3 wherein the second processor further comprises a device for merging the preselected portion of the particular data block modified by the first processor with a remainder of the particular data block stored in the write-back cache of the second processor, storing a merged data block in the write-back cache of the second processor and clearing the one of the plurality of selectively setable identifiers associated with the particular data block to clear the incomplete state.

Claim 6

The computer system according to claim 1 wherein the first and second processors of the plurality of processors are arranged to cooperate together to function as a processor pair.

Claim 7

The computer system according to claim 1 wherein the read request is a read command.

Claim 8

The computer system according to claim 1 wherein the read request is a read for ownership command.

Claim 9

A computer system comprising: a plurality of processors having at least one processor pair, each of one of the plurality of processors including a write-back cache for temporary storing of copies of preselected data blocks, the plurality of processors being coupled to each other by a first bus; a central memory control mechanism; each one of the plurality of processors being coupled by the first bus to the central memory control mechanism; the central memory control mechanism being coupled to a main memory module by a second bus, the main memory module stores data; a plurality of selectively setable identifiers, each one of the plurality of selectively setable identifiers associated with a respective copy of the preselected data blocks stored in the write-back caches of the plurality of processors; each one of the plurality of selectively setable identifiers being selectively set to indicate a block incomplete state of the copy of the preselected data blocks associated with said one of the plurality of selectively setable identifiers; a first processor of a processor pair of the plurality of processors transmits a read request on the first bus when the first processor preselects a particular data block for temporary storing a copy thereof in the write back cache of the first processor in an owned state; and a second processor of the processor pair of the plurality of processors transmits a preselected portion of the particular data block requested by the first processor on the first bus when the particular data block is stored in the write-back cache of the second processor in the owned state, thereby giving partial ownership to the portion of the particular data block to the first processor, and said second processor sets the one of the plurality of selectively setable identifiers associated with the particular data block to indicate the block incomplete state of the particular data block.

Claim 10

A computer system comprising: a plurality of processors having at least one processor pair, each of one of the plurality of processors including a write-back cache for temporary storing of copies of preselected data blocks, the plurality of processors being coupled to each other by a first bus; a central memory control mechanism; each one of the plurality of processors being coupled by the first bus to the central memory control mechanism; the central memory control mechanism being coupled to a main memory module by a second bus, the main memory module stores data; a plurality of selectively setable identifiers, each one of the plurality of selectively setable identifiers associated with a respective copy of the preselected data blocks stored in the write-back caches of the plurality of processors; each one of the plurality of selectively setable identifiers being selectively set to indicate a block incomplete state of the copy of the preselected data blocks associated with said one of the plurality of selectively setable identifiers; a first processor of a processor pair of the plurality of processors transmits a read request on the first bus when the first processor preselects a particular data block for temporary storing a copy thereof in the write back cache of the first processor in an owned state; and a second processor of the processor pair of the plurality of processors transmits a preselected portion of the particular data block requested by the first processor on the first bus when the particular data block is stored in the write-back cache of the second processor in the owned state, thereby giving partial ownership to the portion of the particular data block to the first processor, and said second processor sets the one of the plurality of selectively setable identifiers associated with the particular data block to indicate the block incomplete state of the particular data block.

Claim 11

The computer system according to claim 8 wherein the first processor further comprises a write buffer for temporary storage of the portion of the particular data block transmitted by the second processor after the portion of the particular data block has been modified by the first processor.

Claim 12

The computer system according to claim 8 wherein the first and second processors are coupled by a second bus and wherein the second processor further comprises a write buffer for temporary storage of the portion of the particular data block after the portion of the particular data block has been modified by the first processor and transmitted by the first processor across the second bus to the second processor.

Claim 13

The computer system of claim 10 wherein the second processor further comprises a device for merging the preselected portion of the particular data block modified by the first processor with a remainder of the particular data block stored in the write-back cache of the second processor, storing a merged data block in the writeback cache of the second processor and clearing the one of the plurality of selectively setable identifiers associated with the particular data block to clear the incomplete state.

Claim 14

The computer system according to claim 8 wherein the first and second processors of the plurality of processors are arranged to cooperate together to function as a processor pair.

Claim 15

The computer system according to claim 8 wherein the read request is a read command.

Claim 16

The computer system according to claim 8 wherein the read request is a read for ownership command.

Claim 19

The method of claim 15 wherein the first processor requires access to the preselected data block further comprising the steps of: (a) operating the first processor to receive the preselected portion of the preselected data block transmitted from the second processor; (b) operating the first processor to detect that the preselected portion of the preselected data block was transmitted by the second processor; (c) operating the first processor to set an incomplete data block identifier for the preselected portion of the preselected data block it received from the second processor; and (d) operating the first processor to store the preselected portion of the preselected data block in the write-back cache of the first processor.

Claim 20

The method of claim 15 wherein the first processor requires access to a remainder of the preselected data block, further comprising the steps of: (a) operating the first processor to transmit a second read request on the first bus requesting the preselected data block; (b) operating the first processor and the second processor to determine if the preselected portion of the preselected data block has been modified by the first processor; (c) when the preselected portion of the preselected data block has not been modified by the first processor, operating the first processor to transmit a status signal on the second bus to the second processor to inform the second processor that the preselected portion of the preselected data block has not been updated; (d) operating the second processor to process the second read request in the second processor to determine if the preselected data block is stored in the write-back cache of the second processor; (e) operating the second processor to clear the incomplete data block identifier for the preselected data block; and (f) operating the second processor to transmit the preselected data block on the first bus to the first processor.

Claim 21

The method of claim 15 wherein the first processor requires access to a remainder of the preselected data block, further comprising the steps of: (a) operating the first processor to transmit a second read request on the first bus requesting the preselected data block; (b) operating the first processor and the second processor to determine if the preselected portion of the preselected data block has been modified by the first processor; (c) when the preselected portion of the preselected data block has been modified by the first processor, operating the first processor to transmit the modified preselected portion of the preselected data block on the second bus to the second processor; (d) operating the second processor to merge the preselected portion of the preselected data block received from the first processor with the remainder of the preselected data block stored in the write-back cache of the second processor; (e) operating the second processor to process the second read request in the second processor to determine if the preselected data block is stored in the write-back cache of the second processor; (f) operating the second processor to clear the incomplete data block identifier for the preselected data block; and (g) operating the second processor to transmit the preselected data block on the first bus to the first processor and operating the second processor to relinquish ownership of the preselected data block to the first processor.

Claim 22

The method of claim 15 wherein a third processor of the plurality of processors requires access to the preselected data block, further comprising the steps of: (a) operating the third processor to transmit a read for ownership request on the first bus requesting ownership of the preselected data block; (b) operating the first processor and the second processor to identify that the preselected portion of the preselected data block is stored in the write-back cache of the first processor and the preselected data block is stored in the write-back cache of the second processor as an incomplete data block; (c) operating the first processor and the second processor to determine if the preselected portion of the preselected data block has been modified by the first processor; (d) when the preselected portion of the preselected data block has not been modified by the first processor, operating the first processor to transmit a status signal on the second bus to the second processor to inform the second processor that the preselected portion of the preselected data block has not been updated; (e) operating the second processor to clear the incomplete data block identifier for the preselected data block; and (f) operating the second processor to transmit the preselected data block on the first bus from the second processor to the third processor and operating the second processor to relinquish ownership of the preselected data block to the third processor.

Claim 23

The method of claim 15 wherein a third processor of the plurality of processors requires access to the preselected data block, further comprising the steps of: (a) operating the third processor to transmit a read for ownership request on the first bus requesting ownership of the preselected data block; (b) operating the first processor and the second processor to determine that the preselected portion of the preselected data block is stored in the write-back cache of the first processor and the preselected data block is stored in the write-back cache of the second processor as an incomplete data block; (c) operating the first processor and the second processor to determine if the preselected portion of the preselected data block has been modified by the first processor; (d) when the preselected portion of the preselected data block has been modified by the first processor, operating the first processor to transmit the preselected portion of the preselected data block on the second bus to the second processor; (e) operating the second processor to merge the preselected portion of the preselected data block received from the first processor with a remainder of the preselected data block stored in the write-back cache of the second processor; (f) operating the second processor to clear the incomplete data block identifier for the preselected data block; and (g) operating the second processor to transmit the preselected data block on the first bus from the second processor to the third processor and operating the second processor to relinquish ownership of the preselected data block to the third processor.

Claim 24

The method of claim 15 wherein a third processor of the plurality of processors requires access to the preselected data block, further comprising the steps of: (a) operating the third processor to transmit a read request on the first bus from the third processor requesting the preselected data block; (b) operating the first processor and the second processor to determine that the preselected portion of the preselected data block is stored in the write-back cache of the first processor and the preselected data block is stored in the write-back cache of the second processor as an incomplete data block; (c) operating the first processor and the second processor to determine if the preselected portion of the preselected data block has been modified by the first processor; (d) when the preselected portion of the preselected data block has not been modified by the first processor, operating the first processor to transmit a status signal on the second bus to the second processor to inform the second processor that the preselected portion of the preselected data block has not been updated; (e) operating the second processor to clear the incomplete data block identifier for the preselected data block; and (f) operating the second processor to transmit the preselected data block on the first bus from the second processor to the third processor and operating the second processor to share ownership of the preselected data block with the third processor.

Claim 25

The method of claim 15 wherein a third processor of the plurality of processors requires access to the preselected data block, further comprising the steps of: (a) operating the third processor to transmit a read request on the first bus requesting the preselected data block; (b) operating the first processor and the second processor to identify that the preselected portion of the preselected data block is stored in the write-back cache of the first processor and the preselected data block is stored in the write-back cache of the second processor as an incomplete data block; (c) operating the first processor and the second processor to determine if the preselected portion of the preselected data block has been modified by the first processor; (d) when the preselected portion of the preselected data block has been modified by the first processor, operating the first processor to transmit the preselected portion of the preselected data block on the second bus to the second processor; (e) operating the second processor to merge the preselected portion of the preselected data block received from the first processor with a remainder of the preselected data block stored in the write-back cache of the second processor; (f) operating the second processor to clear the incomplete data block identifier for the preselected data block; and (g) operating the second processor to transmit the preselected data block on the first bus from the second processor to the third processor and operating the second processor to share ownership of the preselected data block to the third processor.

Claim 26

The method of claim 15 wherein the step of operating the first processor to transmit a read request comprises operating the first processor to transmit a read command.

Claim 27

The method of claim 15 wherein the step of operating the first processor to transmit a read request comprises operating the first processor to transmit a read for ownership command.

Claim 30

The method of claim 15 wherein after the substep of operating the second processor to set a second identifier, the method further comprising the steps of: (a) operating the second processor to determine that it requires access to the preselected data block; (b) operating the second processor to determine if the preselected data block is stored in the write-back cache of the second processor; (c) upon determining that the preselected data block is stored in the write-back cache of the second processor, operating the second processor to determine if the preselected data block is part of an incomplete data block; (d) upon determining that the preselected data block is part of an incomplete data block, operating the second processor to determine if data in the preselected data block required by the second processor is stored in the write-back cache of the second processor; and (e) upon determining that the data in the preselected data block required by the second processor is stored in the write-back cache of the second processor, operating the second processor to access the preselected data block.

Claim 31

The method of claim 15 wherein after the substep of operating the second processor to set a second identifier, the method further comprising the steps of: (a) operating the second processor to determine that it requires access to the preselected data block; (b) operating the second processor to determine if the preselected data block is stored in the write-back cache of the second processor; (c) upon determining that the preselected data block is stored in the write-back cache of the second processor, operating the second processor to determine if the preselected data block is part of an incomplete data block; (d) upon determining that the preselected data block is part of an incomplete data block, operating the second processor to determine if data in the preselected data block required by the second processor is stored in the write-back cache of the second processor; (e) upon determining that the data in the preselected data block required by the second processor is not stored in the write-back cache of the second processor, operating the second processor to transmit a read request on the first bus requesting the preselected data block; operating the first processor to determine if the preselected portion of the preselected data block has been modified by the first processor; (f) operating the first processor to determine if the preselected portion of the preselected data block has been modified by the first processor; (g) when the preselected portion of the preselected data block has not been modified by the first processor, operating the first processor to transmit a status signal on the second bus to the second processor to inform the second processor that the preselected portion of the preselected data block has not been updated; (h) operating the first processor to invalidate the incomplete data block identifier in the first processor for the preselected portion of the preselected data block stored in the write-back cache of the first processor; and (i) operating the second processor to invalidate the incomplete data block identifier in the second processor for the preselected data block stored in the write-back cache of the second processor.

Claim 32

The method of claim 15 wherein after the substep of operating the second processor to set a second identifier, the method further comprising the steps of: (a) operating the second processor to determine that it requires access to the preselected data block; (b) operating the second processor to determine if the preselected data block is stored in the write-back cache of the second processor; (c) upon determining that the preselected data block is stored in the write-back cache of the second processor, operating the second processor to determine if the preselected data block is part of an incomplete data block; (d) upon determining that the preselected data block is part of an incomplete data block, operating the second processor to determine if data in the preselected data block required by the second processor is stored in the write-back cache of the second processor; (e) upon determining that the data in the preselected data block required by the second processor is not stored in the write-back cache of the second processor, operating the second processor to transmit a read request on the first bus requesting the preselected data block; (f) operating the first processor to determine if the preselected portion of the preselected data block has been modified by the first processor; (g) when the preselected portion of the preselected data block has been modified by the first processor, operating the first processor to transmit the preselected portion of the preselected data block on the second bus to the second processor; (h) operating the second processor to merge the preselected portion of the preselected data block received from the first processor with the remainder of the preselected data block stored in the write-back cache of the second processor; (i) operating the second processor to store a merged preselected data block in the write-back cache of the second processor; and (j) operating the first processor to invalidate the incomplete data block identifier in the first processor for the preselected portion of the preselected data block stored in the write-back cache of the first processor and (k) operating the second processor to invalidate the incomplete data block identifier in the second processor for the preselected data block stored in the write-back cache of the second processor.