Buffer control system

Claim 1

A buffer control apparatus for controlling delivery of data from a processing unit equipped with a buffer device to a main store, comprising: write command request means for generating a write command request signal, a write address signal, a write data signal and a write location specify signal; store means for storing the write address signal, the write data signal and the write location specify signal which are supplied thereto from said write command request means; counter means for responding to the write command request signal from the write command request means by incrementing at a predetermined time interval; command signal generator means for generating a command signal when said counter means reaches a predetermined value; comparator means for comparing a last write address stored in the store means before the command signal generator means generates the command signal and an address of a subsequent request; merging means for writing subsequent write data over preceding write data stored in the store means in response to a coincidence output of the comparator means and according to a write command by a subsequent request having a write address which is coincident with the last write address; and data read command means for delivering a command for reading data out of the store means in response to the command signal from the command signal generator means.