Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions

Claim 1

A method for concurrently issuing and executing a pair of instructions, included in a target instruction set, in parallel, said method comprising the steps of: selecting a subset of complex instructions of said target instruction set for concurrent issue and execution; selecting a processor having an architecture that executes a target instruction set, with the target instruction set including complicated instructions executed by microcode routines stored in a micro-store included in the processor; providing resources to said processor for concurrently issuing and executing pairs of complex instructions included in said subset; providing a set of modified microcode routines providing for the concurrent issue and execution of pairs of complex instructions included in said subset; fetching ordered instructions included in a program and providing a pair of adjacent instructions in the program as a first pair of instructions; decoding said first pair of instructions to generate a first pair of decoded results; processing said first pair of decoded results to indicate if said first pair is an included pair that is included in said subset of pairs instructions which can be concurrently issued and executed; concurrently issuing said first pair of complex instructions to be concurrently executed by said modified microcode routines and architecture if said first pair of complex instructions is included in said subset; and utilizing said decoded results to select a modified microcode routine to execute said first pair of complex instructions when said first pair are concurrently issued.

Claim 2

A method for concurrently issuing and executing a pair of instructions, included in a target instruction set, in parallel, said method comprising the steps of: selecting a subset of complex instructions of said target instruction set for concurrent issue and execution; selecting a processor having an architecture that executes a target instruction set, with the target instruction set including complicated instructions executed by microcode routines stored in a micro-store included in the processor; providing resources to said processor for concurrently issuing and executing pairs of complex instructions included in said subset; providing a set of modified microcode routines providing for the concurrent issue and execution of pairs of complex instructions included in said subset; fetching ordered instructions included in a program and providing a pair of adjacent instructions in the program as a first pair of instructions; decoding said first pair of instructions to generate a first pair of decoded results; processing said first pair of decoded results to indicate if said first pair is an included pair that is included in said subset of pairs instructions which can be concurrently issued and executed; concurrently issuing said first pair of complex instructions to be concurrently executed by said modified microcode routines and architecture if said first pair of complex instructions is included in said subset; and utilizing said decoded results to select a modified microcode routine to execute said first pair of complex instructions when said first pair are concurrently issued.

Claim 3

A method for concurrently issuing and executing a pair of instructions in parallel, said method comprising the steps of: selecting an existing processor having an architecture that executes an existing target instruction set and memory locations for storing data; selecting a subset of pairs of instructions of said target instruction set for concurrent issue and execution; including in said subset a MOV/ALU pair of instructions with a first instruction in said MOV/ALU pair for moving data between memory locations and a second instruction in said MOV/ALU pair for performing an arithmetic or logical operation on data held in memory locations; modifying the architecture of said existing processor to form a modified architecture which provides resources for concurrently executing all pairs in said subset; fetching ordered instructions included in a program and providing a pair of adjacent instructions in the program as a first pair of instructions; decoding said first pair of instructions to generate a first pair of decoded results; processing said first pair of decoded results to indicate if said first pair is an included pair that is included in said subset of pairs instructions which can be concurrently issued and executed; concurrently issuing said first pair of instructions to be concurrently executed by said modified architecture only if said first pair is an included pair; and utilizing said first pair decoded results to execute said first pair of instructions if said first pair is concurrently issued.

Claim 4

A method for concurrently issuing and executing a pair of instructions in parallel, said method comprising the steps of: selecting an existing processor having an architecture that executes an existing target instruction set and memory locations for storing data; selecting a subset of pairs of instructions of said target instruction set for concurrent issue and execution; including in said subset a MOV/ALU pair of instructions with a first instruction in said MOV/ALU pair for moving data between memory locations and a second instruction in said MOV/ALU pair for performing an arithmetic or logical operation on data held in memory locations; modifying the architecture of said existing processor to form a modified architecture which provides resources for concurrently executing all pairs in said subset; fetching ordered instructions included in a program and providing a pair of adjacent instructions in the program as a first pair of instructions; decoding said first pair of instructions to generate a first pair of decoded results; processing said first pair of decoded results to indicate if said first pair is an included pair that is included in said subset of pairs instructions which can be concurrently issued and executed; concurrently issuing said first pair of instructions to be concurrently executed by said modified architecture only if said first pair is an included pair; and utilizing said first pair decoded results to execute said first pair of instructions if said first pair is concurrently issued.

Claim 5

A method for concurrently issuing and executing a pair of instructions in parallel, said method comprising the steps of: selecting an existing processor having an architecture that executes an existing target instruction set, with the target instruction set including complicated instructions executed in multiple cycles by microcode routines stored in a micro-store included in the existing processor; selecting a subset of instructions of said target instruction set for concurrent issue and execution; modifying the architecture of said existing processor to form a modified architecture which provides resources, including parallel data paths, for concurrently issuing and executing pairs of instructions included in said subset; modifying the microcode routines of said existing processor to form a set of modified microcode routines for controlling the parallel data paths of said modified architecture to execute pairs of instructions in said subset or said complex instructions; fetching ordered instructions included in a program and providing a pair of adjacent instructions in the program as a first pair of instructions; decoding said first pair of instructions to generate a first pair of decoded results; concurrently issuing said first pair of instructions to be concurrently executed by said modified architecture only if said first pair is an included pair or issuing only a first instruction in said first pair if said first pair is not an included pair; and utilizing said first pair decoded results to execute said first pair of instructions if said first pair is concurrently issued or a microcode routine to execute said first instruction if said first instruction is a complex instruction and only said first instruction is issued.

Claim 6

A method for concurrently issuing and executing a pair of instructions in parallel, said method comprising the steps of: selecting an existing processor having an architecture that executes an existing target instruction set, with the target instruction set including complicated instructions executed in multiple cycles by microcode routines stored in a micro-store included in the existing processor; selecting a subset of instructions of said target instruction set for concurrent issue and execution; modifying the architecture of said existing processor to form a modified architecture which provides resources, including parallel data paths, for concurrently issuing and executing pairs of instructions included in said subset; modifying the microcode routines of said existing processor to form a set of modified microcode routines for controlling the parallel data paths of said modified architecture to execute pairs of instructions in said subset or said complex instructions; fetching ordered instructions included in a program and providing a pair of adjacent instructions in the program as a first pair of instructions; decoding said first pair of instructions to generate a first pair of decoded results; concurrently issuing said first pair of instructions to be concurrently executed by said modified architecture only if said first pair is an included pair or issuing only a first instruction in said first pair if said first pair is not an included pair; and utilizing said first pair decoded results to execute said first pair of instructions if said first pair is concurrently issued or a microcode routine to execute said first instruction if said first instruction is a complex instruction and only said first instruction is issued.

Claim 7

A system for concurrently issuing and executing included pairs of instructions in parallel, with an included pair of instructions comprising first and second instructions included in a first subset of instructions forming a part of a target instruction set of an existing processor, with the existing processor having an architecture that executes the existing target instruction set and memory locations for storing data, with said subset including a MOV instruction and an ALU instruction, with a MOV instruction for moving data between memory locations and an ALU instruction for performing an arithmetic or logical operation on data held in memory locations, said system comprising: a fetch unit for fetching ordered instructions included in a program and providing a pair of adjacent instructions in the program as a first pair of instructions; a decoder for decoding said first pair of instructions to generate a first pair of decoded results; a pairing unit for processing said first pair of decoded results to indicate if said first pair is an included pair that is included in said subset of pairs instructions which can be concurrently issued and executed; means for concurrently issuing said first pair of instructions to be concurrently executed by said modified architecture only if said first pair is an included pair; and a modified architecture includes resources for concurrently executing all included pairs of instructions, with the modified architecture utilizing said first pair of decoded results to execute said first pair of instructions if said first pair is concurrently issued.

Claim 8

A system for concurrently issuing and executing included pairs of instructions in parallel, with an included pair of instructions comprising first and second instructions included in a first subset of instructions forming a part of a target instruction set of an existing processor, with the existing processor having an architecture that executes the existing target instruction set and memory locations for storing data, with said subset including a MOV instruction and an ALU instruction, with a MOV instruction for moving data between memory locations and an ALU instruction for performing an arithmetic or logical operation on data held in memory locations, said system comprising: a fetch unit for fetching ordered instructions included in a program and providing a pair of adjacent instructions in the program as a first pair of instructions; a decoder for decoding said first pair of instructions to generate a first pair of decoded results; a pairing unit for processing said first pair of decoded results to indicate if said first pair is an included pair that is included in said subset of pairs instructions which can be concurrently issued and executed; means for concurrently issuing said first pair of instructions to be concurrently executed by said modified architecture only if said first pair is an included pair; and a modified architecture includes resources for concurrently executing all included pairs of instructions, with the modified architecture utilizing said first pair of decoded results to execute said first pair of instructions if said first pair is concurrently issued.

Claim 9

A system for concurrently issuing and executing included pairs of instructions in parallel, with an included pair of instructions comprising first and second instructions included in a first subset of instructions forming a part of a target instruction set of an existing processor having an architecture that executes the existing target instruction set and memory locations for storing data, with the target instruction set including complicated instructions executed in multiple cycles by microcode routines stored in a micro-store included in the existing processor, said system comprising: a micro-store holding a set of modified microcode routines for controlling the parallel data paths of a modified architecture to execute pairs of instructions in said subset or said complex instructions; a fetch unit for fetching ordered instructions included in a program and providing a pair of adjacent instructions in the program as a first pair of instructions; a decoder for decoding said first pair of instructions to generate a first pair of decoded results; a pairing unit for processing said first pair of decoded results to indicate if said first pair is an included pair that is included in said subset of pairs instructions which can be concurrently issued and executed; means for concurrently issuing said first pair of instructions to be concurrently executed by said modified architecture only if said first pair is an included pair or issuing only a first instruction in said first pair if said first pair is not an included pair; and a modified architecture which provides resources, including parallel data paths, for concurrently issuing and executing pairs of instructions included in said subset that utilizes said first pair of decoded results to execute said first pair of instructions if said first pair is concurrently issued or a microcode routine to execute said first instruction if said first instruction is a complex instruction and only said first instruction is issued.

Claim 10

A system for concurrently issuing and executing included pairs of instructions in parallel, with an included pair of instructions comprising first and second instructions included in a first subset of instructions forming a part of a target instruction set of an existing processor having an architecture that executes the existing target instruction set and memory locations for storing data, with the target instruction set including complicated instructions executed in multiple cycles by microcode routines stored in a micro-store included in the existing processor, said system comprising: a micro-store holding a set of modified microcode routines for controlling the parallel data paths of a modified architecture to execute pairs of instructions in said subset or said complex instructions; a fetch unit for fetching ordered instructions included in a program and providing a pair of adjacent instructions in the program as a first pair of instructions; a decoder for decoding said first pair of instructions to generate a first pair of decoded results; a pairing unit for processing said first pair of decoded results to indicate if said first pair is an included pair that is included in said subset of pairs instructions which can be concurrently issued and executed; means for concurrently issuing said first pair of instructions to be concurrently executed by said modified architecture only if said first pair is an included pair or issuing only a first instruction in said first pair if said first pair is not an included pair; and a modified architecture which provides resources, including parallel data paths, for concurrently issuing and executing pairs of instructions included in said subset that utilizes said first pair of decoded results to execute said first pair of instructions if said first pair is concurrently issued or a microcode routine to execute said first instruction if said first instruction is a complex instruction and only said first instruction is issued.

Claim 11

A system for concurrently issuing and executing included pairs of instructions in parallel, with an included pair of instructions comprising first and second instructions included in a subset of instructions forming part of a target instruction set, said system comprising: a micro-store holding a set of modified microcode routines providing for the concurrent issue and execution of pairs of complex instructions included in said subset; a fetch unit for fetching ordered instructions included in a program and providing a pair of adjacent instructions in the program as a first pair of instructions; a decoder for decoding said first pair of instructions to generate a first pair of decoded results; a pairing unit for processing said first pair of decoded results to indicate if said first pair is an included pair; a stage, responsive to said pairing unit, for concurrently issuing said first pair of complex instructions to be concurrently executed by said modified microcode routines and architecture if said first pair of complex instructions is included in said subset; and an architecture that executes the target instruction set, with the target instruction set including complicated instructions executed by microcode routines stored in a micro-store included in the processor, with the architecture including resources for concurrently issuing and executing pairs of complex instructions included in said subset, with the architectur utilizing said decoded results to select a modified microcode routine to execute said first pair of complex instructions when said first pair are concurrently issued.

Claim 12

A system for concurrently issuing and executing included pairs of instructions in parallel, with an included pair of instructions comprising first and second instructions included in a subset of instructions forming part of a target instruction set, said system comprising: a micro-store holding a set of modified microcode routines providing for the concurrent issue and execution of pairs of complex instructions included in said subset; a fetch unit for fetching ordered instructions included in a program and providing a pair of adjacent instructions in the program as a first pair of instructions; a decoder for decoding said first pair of instructions to generate a first pair of decoded results; a pairing unit for processing said first pair of decoded results to indicate if said first pair is an included pair; a stage, responsive to said pairing unit, for concurrently issuing said first pair of complex instructions to be concurrently executed by said modified microcode routines and architecture if said first pair of complex instructions is included in said subset; and an architecture that executes the target instruction set, with the target instruction set including complicated instructions executed by microcode routines stored in a micro-store included in the processor, with the architecture including resources for concurrently issuing and executing pairs of complex instructions included in said subset, with the architectur utilizing said decoded results to select a modified microcode routine to execute said first pair of complex instructions when said first pair are concurrently issued.