EP0118830A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Pipelined processor
Assignee: International Business Machines Corp
•
Filing: 1984-02-29
•
Granted: —
•
Expires: 2004-02-29
Abstract
Abstract A pair of inherently sequential instructions, having an instruction dependency of the type in which the subsequent instruction requires as an input operand the result of the earlier instruction execution, can nevertheless be simultaneously executed by two data flow facilities (primary and secondary) under control of a control unit, without the requirement that both data flow facilities be fully equipped for all instructions. The secondary data flow facility of this invention is generally less massive and less sophisticated than the primary data flow facility but is more sophisticated in a critical organ, the adder. The adder in the secondary data flow facility has one additional operand capability. The three-input adder of the secondary data flow facility thus is capable of replicating internally a result of the two-input adder of the primary data flow facility. Using this replicated primary adder "result", together with the additional operand capability, the secondary data flow facility three- input adder executes the dependent subsequent instruction of the pair simultaneously with the earlier instruction execution by the primary data flow facility.
Inventors
- 👤 Hsieh Tung Hao
- 👤 Huei Ling
- 👤 Howard Edward Sachar
- 👤 Jeffrey Weiss
- 👤 Yannis John Yamour
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 11:34
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F9/3889; G06F9/3836; G06F9/3853
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
252 words
A pipelined processor including a pipeline instruction control unit and one or more data flow facilities, each operable to process a stream of instructions defined by the instruction control unit -- -- characterized by -- a) one or more secondary data flow facilities each having a capability different from a required reference capability of a primary data flow facility, said secondary data flow facility comprising at least one critical organ having at least one quantum capability increment over the required reference capability of the comparable organ of the primary data flow facilities, so that the secondary data flow facilities can process all the inputs required to replicate internally the apparent result of processing by the equivalent organ of the primary data flow facility and previous secondary data flow facilities as a subset of its input set; b) an instruction unit comprising means to detect adjacent instruction groups including: interlocked instruction sequences where one adjacent instruction necessarily must be delayed pending completion of another; adjacent instruction sequences in which one of a group of adjacent instructions requires operand inputs including an operand input which is the result of processing the operand inputs for another instruction of the group; and independent adjacent instruction sequences which require unrelated operand inputs; , c. control means associated operatively with said instruction unit and said primary and secondary data flow facilities to control simultaneous processing of dependent adjacent instruction sequences and independent adjacent instruction sequences, and to delay processing of appropriate instructions when necessary in interlocked instruction sequences.
Claim 2
Dependent Claim
252 words
A pipelined processor including a pipeline instruction control unit and one or more data flow facilities, each operable to process a stream of instructions defined by the instruction control unit -- -- characterized by -- a) one or more secondary data flow facilities each having a capability different from a required reference capability of a primary data flow facility, said secondary data flow facility comprising at least one critical organ having at least one quantum capability increment over the required reference capability of the comparable organ of the primary data flow facilities, so that the secondary data flow facilities can process all the inputs required to replicate internally the apparent result of processing by the equivalent organ of the primary data flow facility and previous secondary data flow facilities as a subset of its input set; b) an instruction unit comprising means to detect adjacent instruction groups including: interlocked instruction sequences where one adjacent instruction necessarily must be delayed pending completion of another; adjacent instruction sequences in which one of a group of adjacent instructions requires operand inputs including an operand input which is the result of processing the operand inputs for another instruction of the group; and independent adjacent instruction sequences which require unrelated operand inputs; , c. control means associated operatively with said instruction unit and said primary and secondary data flow facilities to control simultaneous processing of dependent adjacent instruction sequences and independent adjacent instruction sequences, and to delay processing of appropriate instructions when necessary in interlocked instruction sequences.
Claim 3
Dependent Claim
228 words
A pipelined processor including a pipeline instruction control unit and a primary data flow facility operable to process a stream of instructions defined by the instruction control unit -- characterized by -- a) a secondary data flow facility having a required capability different from a reference capability of the primary data flow facility, said primary data flow facility comprising an (n)-input adder, while the secondary data flow facility comprises a comparable (2n-l)- input adder so that the secondary data flow (2n-l)-input adder can process all the inputs required to replicate internally the apparent result of processing by the (n)-input adder of the primary data flow facility as partial input of its input set; b) an instruction unit comprising means to detect adjacent instruction groups including: interlocked instruction sequences where one adjacent instruction necessarily must be delayed pending completion of another; adjacent instruction sequences in which one of a group of adjacent instructions requires operand inputs including an operand input which is the result of processing the operand inputs for another instruction of the group; and independent adjacent instruction sequences which require unrelated operand inputs; c. control means associated operatively with said instruction unit and said primary and secondary data flow facilities to control simultaneous processing of dependent adjacent instruction sequences and independent adjacent instruction sequences, and to delay processing of appropriate instructions when necessary in interlocked instruction sequences.
Claim 4
Dependent Claim
228 words
A pipelined processor including a pipeline instruction control unit and a primary data flow facility operable to process a stream of instructions defined by the instruction control unit -- characterized by -- a) a secondary data flow facility having a required capability different from a reference capability of the primary data flow facility, said primary data flow facility comprising an (n)-input adder, while the secondary data flow facility comprises a comparable (2n-l)- input adder so that the secondary data flow (2n-l)-input adder can process all the inputs required to replicate internally the apparent result of processing by the (n)-input adder of the primary data flow facility as partial input of its input set; b) an instruction unit comprising means to detect adjacent instruction groups including: interlocked instruction sequences where one adjacent instruction necessarily must be delayed pending completion of another; adjacent instruction sequences in which one of a group of adjacent instructions requires operand inputs including an operand input which is the result of processing the operand inputs for another instruction of the group; and independent adjacent instruction sequences which require unrelated operand inputs; c. control means associated operatively with said instruction unit and said primary and secondary data flow facilities to control simultaneous processing of dependent adjacent instruction sequences and independent adjacent instruction sequences, and to delay processing of appropriate instructions when necessary in interlocked instruction sequences.
Claim 5
Dependent Claim
36 words
A pipelined processor according to Claim 2, in which said (n)-input adder of said secondary data flow facility is a three-input adder and the comparable organ in the primary data flow facility is a two-input adder.
Claim 6
Dependent Claim
61 words
A pipelined processor according to Claim 3, further characterized by: means providing first and second operands to the two-input adder, to produce a third operand result, and means simultaneously providing first, second and fourth operands to said threeinput adder, whereby said three-input adder computes the algebraic result of inputs including the apparent third operand result of computation by the two-input adder.
Claim 7
Dependent Claim
61 words
A pipelined processor according to Claim 1, further characterized in that the first of a plurality of data flow facilities is equipped to process [(n)] inputs; and additional data flow facilities, in sequence by complexity, are equipped to process [(n)+(k-l) (n-1)] inputs, where (n) is the number of inputs to the minimum facility and (k) is the facility sequence position number.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.