EP0155211A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
System for by-pass control in pipeline operation of computer
Assignee: Fujitsu Ltd
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Filing: 1985-02-25
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Granted: —
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Expires: 2005-02-25
Abstract
Abstract A system for computer pipeline operation, in which a plurality of instructions are executed in parallel by commencing, before the termination of execution of the preceding instruction, the execution of the present instruction, includes a conflict detection unit (3), a data establishment indication unit (41, 42), and a source data by-pass unit (62, 64, 66,67). The source data by-pass unit by-passes a source data to the processing stage which requires this source data immediately after conflict is detected between the result data of the preceding instruction and the source data of the present instruction and the establishment of the source data of the present instruction is detected.
Inventors
- 👤 Toshiaki Kitamura
- 👤 Yuji Oinaga
- 👤 Katsumi Onishi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 08:42
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3824
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
154 words
A system for by-pass control in pipeline operation of a computer, using a plurality of processing stages, an instruction being executed in a plurality of periods, a plurality of instructions being executed in parallel by commencing, before the termination of execution of the preceding.instruction, the execution of the present instruction, said system comprising: a conflict detection means for detecting conflict between the result data of the preceding instruction and the source data of the present instruction, a data establishment indication means for indicating the establishment of the result data of the preceding instruction prior to the usual result writing period, and a source data by-pass means for by-passing a source data to the processing stage which requires this source data immediately after conflict is detected between the result data of the preceding instruction and the source data of the present instruction and the establishment of the source data of the present instruction is detected.
Claim 2
Independent Claim
154 words
A system for by-pass control in pipeline operation of a computer, using a plurality of processing stages, an instruction being executed in a plurality of periods, a plurality of instructions being executed in parallel by commencing, before the termination of execution of the preceding.instruction, the execution of the present instruction, said system comprising: a conflict detection means for detecting conflict between the result data of the preceding instruction and the source data of the present instruction, a data establishment indication means for indicating the establishment of the result data of the preceding instruction prior to the usual result writing period, and a source data by-pass means for by-passing a source data to the processing stage which requires this source data immediately after conflict is detected between the result data of the preceding instruction and the source data of the present instruction and the establishment of the source data of the present instruction is detected.
Claim 3
Dependent Claim
75 words
A system according to claim 1, wherein said processing stages include an operand address calculation stage, an operand data fetch stage, a calculation execution stage, and a result writing stage, and said conflict detection means detects conflict between the register into which the result of the execution of the preceding instruction is to be written and the register from which the data necessary for the address calculation for the present instruction is to be read.
Claim 4
Dependent Claim
43 words
A system according to claim 1, wherein said data establishment indication means indicates the fact that, in a specific instruction, the data to be written in the result writing execution period is the data which is established in the address calculation execution period.
Claim 5
Dependent Claim
119 words
A system according to claim 1, wherein said process stages include an operand address calculation circuit for calculating an operand address; and an operand address holding circuit for holding said calculated operand address; the control being carried out in such a manner that, when a register conflict occurs concerning the input data used for the address calculation in pipeline operation of a computer, under the condition that the preceding instruction is an instruction which can define the content of the data to be written into the register by a calculation circuit for calculating the operand address, the data for calculation of the operand address for the present instruction is supplied via a by-pass from the operand address holding circuit.
Claim 6
Dependent Claim
190 words
A system according to claim 1, wherein said processing stages include an operand address calculation circuit for calculating an operand address; a plurality of by-pass registers, the number of said by-pass registers being dependent on the number of the pipeline stages to which the result of the calculation in said operand address calculation circuit are registered; a coincidence circuit for detecting the register conflicts in the pipeline operation; and a by-pass permission data storage circuit for storing by-pass permission data in accordance with the kinds of instruction in correspondence with each of said by-pass registers; the control being carried out in such a manner that, when a register conflict occurs concerning the input data used for the address calculation in pipeline operation of a computer, under the condition that the preceding instruction is an instruction which can define the content of the data written into the register by the data from said operand address calculation circuit or the data read from a storage portion, the data for base modification or index modification in the operand address calculation for the present instruction is supplied via a by-pass from said by-pass registers.
References Cited (Backward Citations)
No citation records indexed.
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