Pipeline-controlled data processing system capable of performing a plurality of instructions simultaneously

Claim 2

A pipeline controlled data processing system for executing instructions, wherein each instruction is executed in a plurality of sequential stages with the sequential stages of first and second consecutive instructions overlapping in time with one another and wherein the last stage of execution of each instruction is an execution cycle, each of said instructions having an address portion, said system including a register means to be loaded with an execution result in response to an instruction, and memory means having a plurality of locations, said data processing system further comprising: instruction prefetch means connected to said memory means for prefetching instructions from said memory means and decoding said instructions; first detection means connected to said instruction prefetch means for detecting that the execution cycle of a first instruction requires more than one machine cycle to be performed and for detecting that said first instruction instructs the generation of a first execution result and the loading of said first execution result into said register means; second detection means connected to said instruction prefetch means for detecting that a second instruction, following said first instruction and prefetched by said instruction prefetch means prior to completion of the execution of said first instruction, requires fewer machine cycles to be performed than said first instruction and instructs the storing of said first execution result from said register means into a location of said memory means designated by said address of said second instruction; control means responsive to said first and second detection means for supplying a control signal before the completion of said first instruction; and execution means responsive to said control signal for storing said first execution result into the location of said memory means designated by said address of said second instruction and simultaneously with the loading of said first execution result into said register means in accordance with said first instruction, to thereby complete the execution of said first and second instructions at the same time.

Claim 3

A pipeline controlled data processing system for executing instructions, wherein each instruction is executed in a plurality of sequential stages with the sequential stages of first and second consecutive instructions overlapping in time with one another and wherein the last stage is an execution cycle, each of said instructions having an address portion, said systems including register means to be loaded with an execution result in response to an instruction, and memory means having a plurality of locations, said data processing system further comprising: instruction prefetch means connected to said memory means for prefetching instructions from said memory means and for decoding said instructions; first detection means connected to said instruction prefetch means for detecting that the execution cycle of a first instruction requires more than two machine cycles to be performed and that said first instruction instructs the generation of a first execution result and the loading of a first execution result into said register means; second detection means connected to said instruction prefetch means for detecting that a second instruction, following said first instruction and prefetched by said instruction prefetch means prior to completion of the execution of said first instruction, requires fewer machine cycles to be performed than said first instruction and instructs the storing of said first execution result from said register means into a location of said memory means designated by said address of said second instruction; third detection means connected to said instruction prefetch means for detecting that a third instruction, following said second instruction and prefetched by said instruction prefetch means prior to completion of the execution of said first instruction, requires fewer machine cycles to be performed than said first instruction and instructs the loading of the contents of a location of said memory means designated by said address of said third instruction into said register means; control means responsive to said first, second and third detection means for supplying a control signal before the completion of said first instruction; and execution means responsive to said control signal for storing said first execution result into the location of said memory means designated by said address of said second instruction and simultaneously loading the contents of said location of said memory means designated by said address of said third instruction into said register means, to thereby complete the execution of said first, second and third instructions at the same time.

Claim 4

A pipeline controlled data processing system for executing instructions, wherein each instruction is executed in a plurality of sequential stages with the sequential stages of first and second consecutive instructions overlapping in time with one another and wherein the last stage is an execution cycle, each of said instructions having an address portion, said systems including register means to be loaded with an execution result in response to an instruction, and memory means having a plurality of locations, said data processing system further comprising: instruction prefetch means connected to said memory means for prefetching instructions from said memory means and for decoding said instructions; first detection means connected to said instruction prefetch means for detecting that the execution cycle of a first instruction requires more than two machine cycles to be performed and that said first instruction instructs the generation of a first execution result and the loading of a first execution result into said register means; second detection means connected to said instruction prefetch means for detecting that a second instruction, following said first instruction and prefetched by said instruction prefetch means prior to completion of the execution of said first instruction, requires fewer machine cycles to be performed than said first instruction and instructs the storing of said first execution result from said register means into a location of said memory means designated by said address of said second instruction; third detection means connected to said instruction prefetch means for detecting that a third instruction, following said second instruction and prefetched by said instruction prefetch means prior to completion of the execution of said first instruction, requires fewer machine cycles to be performed than said first instruction and instructs the loading of the contents of a location of said memory means designated by said address of said third instruction into said register means; control means responsive to said first, second and third detection means for supplying a control signal before the completion of said first instruction; and execution means responsive to said control signal for storing said first execution result into the location of said memory means designated by said address of said second instruction and simultaneously loading the contents of said location of said memory means designated by said address of said third instruction into said register means, to thereby complete the execution of said first, second and third instructions at the same time.