System and method for cascading multiple programmable interrupt controllers utilizing separate bus for broadcasting interrupt request data packet in a multi-processor system

Claim 1

A multi-processor system comprising: a first bus coupled to said at least one processor; a first I/O device operable to generate a first interrupt request signal when an interrupt is pending thereon; a first interrupt controller, coupled to said first I/O device and having a first device type value and a predetermined identification number, operable to generate a second interrupt request signal in response to said first interrupt request signal: a second interrupt controller, coupled to said first bus and to said first interrupt controller, operable to broadcast an interrupt request data packet on said first bus in response to said second interrupt request signal, said interrupt request data packet comprising a second field set to said first device type value and a third field set to said predetermined identification number; a second I/O device, having a second device type value and coupled to said second interrupt controller, operable to send a third interrupt request signal to said second interrupt controller when an interrupt request is pending on said second I/O device, said second interrupt controller being further overable to broadcast said interrupt request data packet in response to said third interrupt request signal, said second field in said interrupt request data packet being set to said second device type value and said third field therein being set to a second interrupt vector corresponding to said second I/O device and identifying an interrupt service routine to process said interrupt pending on said second I/O device; a processor operable to identify said first interrupt controller based on said second field and said third field; a communication device coupled to said first interrupt controller; and a second bus coupled to said processor and said communication device.

Claim 8

A method of processing interrupts in a multi-processor system comprising: a first I/O device generating a first interrupt request signal when an interrupt is pending therefrom; a first interrupt controller generating a second interrupt request signal in response to said first interrupt request signal; a second interrupt controller broadcasting an interrupt request data packet on a first bus in response to said second interrupt request signal, said interrupt request data packet comprising a second field set to a value indicating the device type of said first interrupt controller and a third field set to a value identifying said first interrupt controller; a processor receiving said interrupt request data packet from said bus, identifying said first interrupt controller based on said second field and said third field, requesting and receiving a first interrupt service vector from said first interrupt controller on a second bus, and using a first interrupt service routine corresponding to said first interrupt service vector to process said interrupt pending on said first I/O device; a second I/O device sending a third interrupt request signal to said second interrupt controller when an interrupt request is pending on said second I/O device; said second interrupt controller broadcasting on said bus said interrupt request data packet in response to said third interrupt request signal, said second field within said interrupt request data packet being set to a value indicating the device type of said second I/O device and said third field therein being set to a second interrupt vector corresponding to said second I/O device; and said processor receiving said interrupt request data packet from said first bus, identifying said second I/O device based on said second field, and using a second interrupt service routine corresponding to said second interrupt service vector extracted from said third field to process said interrupt pending on said second I/O device.

Claim 9

A method of processing interrupts in a multi-processor system comprising: a first I/O device generating a first interrupt request signal when an interrupt is pending therefrom; a first interrupt controller generating a second interrupt request signal in response to said first interrupt request signal; a second interrupt controller broadcasting an interrupt request data packet on a first bus in response to said second interrupt request signal, said interrupt request data packet comprising a second field set to a value indicating the device type of said first interrupt controller and a third field set to a value identifying said first interrupt controller; a processor receiving said interrupt request data packet from said bus, identifying said first interrupt controller based on said second field and said third field, requesting and receiving a first interrupt service vector from said first interrupt controller on a second bus, and using a first interrupt service routine corresponding to said first interrupt service vector to process said interrupt pending on said first I/O device; a second I/O device sending a third interrupt request signal to said second interrupt controller when an interrupt request is pending on said second I/O device; said second interrupt controller broadcasting on said bus said interrupt request data packet in response to said third interrupt request signal, said second field within said interrupt request data packet being set to a value indicating the device type of said second I/O device and said third field therein being set to a second interrupt vector corresponding to said second I/O device; and said processor receiving said interrupt request data packet from said first bus, identifying said second I/O device based on said second field, and using a second interrupt service routine corresponding to said second interrupt service vector extracted from said third field to process said interrupt pending on said second I/O device.