Hierarchical encoder including timing and data detection devices for a content addressable memory

Claim 2

An encoder for use in a content addressable memory having a plurality of content addressable memory subblocks, each of the plurality of content addressable memory subblocks having a plurality of content addressable memory words, the encoder comprising: a priority main encoder that encodes flag data in a word-to-word priority order, the flag data being generated by matching retrieval data with the plurality of the content addressable memory words in each of the plurality of content addressable memory subblocks; and a priority subblock encoder that assigns subblock-to-subblock priorities to the plurality of content addressable memory subblocks, the priority subblock encoder assigning one of the plurality of content addressable memory subblocks as a first priority content addressable subblock and another one of the plurality of content addressable memory subblocks as a second priority content addressable subblock, wherein the priority main encoder comprises: a flag register that stores the flag data of the first priority content addressable memory subblock; and a prefetch circuit that prestores the flag data of the second priority content addressable memory subblock while at least one match signal of the flag data in the flag register is being encoded.

Claim 3

An encoder as claimed in claim 1, further comprising: resetting means for resetting the at least one match signal of the flag data in the flag register, the at least one match signal of one of the plurality of content addressable memory subblocks being sequentially encoded by the priority main encoder, the at least one match signal being reset after being encoded; and detecting means for detecting a termination of the sequential encoding of the at least one match signal of the flag data of the first priority content addressable memory subblock, wherein the priority main encoder sequentially encodes the at least one match signal of the flag data of the second priority content addressable memory subblock when the detection means detects the termination of the sequential encoding of the at least one match signal of the flag data of the first priority content addressable memory subblock.

Claim 4

An encoder as claimed in claim 1, further comprising: resetting means for resetting the at least one match signal of the flag data in the flag register after the at least one match signal of the flag data in the flag register is encoded by the priority main encoder; and a timing detection control circuit that predicts and detects a termination of the encoding of the at least one match signal of the flag data in the flag register and loads the flag data in the prefetch circuit into the flag register when the timing detection control circuit detects the termination of the encoding of the at least one match signal of the flag data in the flag register.

Claim 5

An encoder as claimed in claim 3, wherein the timing detection control circuit includes a number detection circuit comprising: a first signal line; M current driving means for driving current into the first signal line, each of the M current driving means being connected in parallel to the first signal line; M data input lines being connected to the flag register and receiving M bits of the flag data which control the M current driving means; a second signal line; reference current driving means connected to the second signal line; and differential current detecting means for detecting a differential current between current flowing through the first signal line and current flowing through the second signal line, wherein the number detection circuit detects a number of 0's and 1's contained in the M bits of the flag data received from the M data input lines, M and N being integers greater than one.

Claim 6

An encoder as claimed in claim 4, wherein each of the M current driving means comprises: a control transistor that controls an operating timing of the each of the M current driving means; and a signal voltage application transistor, a gate electrode of the signal voltage application transistor being connected to one of the M data input lines.

Claim 7

An encoder as claimed in claim 5, wherein the signal voltage application transistor is connected between the control transistor and the first signal line.

Claim 8

An encoder as claimed in claim 4, wherein the differential current detection means comprises: detection start level setting means for setting a voltage difference between a detection start voltage of the first signal line and a preset voltage and between a detection start voltage of the second signal line and the preset voltage.

Claim 9

An encoder as claimed in claim 4, wherein the timing detection control circuit further includes a first inverter and a second inverter, the first and second inverters being connected between the first signal line and the differential current detection means and between the second signal line and the differential current detection means, respectively.

Claim 10

An encoder as claimed in claim 4, wherein the timing detection control circuit further includes a first transistor and a second transistor, the first and second transistors being connected between the first signal line and the differential current detection means and between the second signal line and the differential current detection means, respectively, at least one first inverter being connected between a gate electrode of the first transistor and the first signal line, and at least one second inverter being connected between a gate electrode of the second transistor and the second signal line.

Claim 11

An encoder as claimed in claim 9, wherein the timing detection control circuit further includes precharging means for precharging connections between the first and second transistors and the differential current detection means.

Claim 12

An encoder as claimed in claim 3, wherein the timing detection control circuit includes a number detection circuit comprising: a first signal line; M unit current driving means for driving current into the first signal line, each of the M unit current driving means being connected in parallel to the first signal line; a data register for holding M bits of data, each of the M bits of data controlling one of the M unit current driving means; a second signal line; N reference unit current driving means for driving current into the second signal line, each of the N reference unit current driving means being connected in parallel to the second signal line; a reference current control register that holds N bits of data, each of the N bits of data controlling one of the reference unit current driving means; reference offset current drive means connected to the second signal line; and differential current detecting means for detecting the differential current between current flowing through the first signal line and the second signal line, a reference current flowing through the second signal line and through the reference offset current drive means, wherein the number detection circuit detects a number of 0's and 1's contained in the M bits of the data held in the data register based on a number of 0's and 1's contained in the N bits of the data held in the reference current control register, M and N being integers greater than one.

Claim 13

An encoder for use in a content addressable memory having a plurality of content addressable memory subblocks, each of the plurality of content addressable memory subblocks having a plurality of content addressable memory words, the encoder comprising: a priority main encoder that encodes flag data in a word-to-word priority order, the flag data being generated by matching retrieval data with the plurality of the content addressable memory words in each of the plurality of content addressable memory subblocks; and a priority subblock encoder that assigns subblock-to-subblock priorities to the plurality of content addressable memory subblocks, the priority subblock encoder assigning one of the plurality of content addressable memory subblocks as a first priority content addressable subblock and another one of the plurality of content addressable memory subblocks as a second priority content addressable subblock, wherein the priority main encoder comprises: a flag register that stores the flag data of the first priority content addressable memory subblock; resetting means for resetting at least one match signal of the flag data in the flag register after the at least one match signal of the flag data in the flag register is encoded by the priority main encoder; a timing detection control circuit that predicts and detects a termination of the encoding of the at least one match signal of the flag data in the flag register and controlling a time when the flag data of the second priority content addressable memory subblock is fed to the flag register based on a prediction by the timing detection control circuit of when the termination of the encoding the at least one match signal of the flag data in the flag register will occur; and a flag data sense circuit that senses the flag data of each of the plurality of the content addressable memory word of a second priority content addressable memory subblock before the termination of the encoding of the at least one match signal of the flag data in the flag register.

Claim 14

An encoder for use in a content addressable memory having a plurality of content addressable memory subblocks, each of the plurality of content addressable memory subblocks having a plurality of content addressable memory words, the encoder comprising: a priority main encoder that encodes flag data in a word-to-word priority order, the flag data being generated by matching retrieval data with the plurality of the content addressable memory words in each of the plurality of content addressable memory subblocks; and a priority subblock encoder that assigns subblock-to-subblock priorities to the plurality of content addressable memory subblocks, the priority subblock encoder assigning one of the plurality of content addressable memory subblocks as a first priority content addressable subblock and another one of the plurality of content addressable memory subblocks as a second priority content addressable subblock, wherein the priority main encoder comprises: a flag register that stores the flag data of the first priority content addressable memory subblock; resetting means for resetting at least one match signal of the flag data in the flag register after the at least one match signal of the flag data in the flag register is encoded by the priority main encoder; a timing detection control circuit that predicts and detects a termination of the encoding of the at least one match signal of the flag data in the flag register and controlling a time when the flag data of the second priority content addressable memory subblock is fed to the flag register based on a prediction by the timing detection control circuit of when the termination of the encoding the at least one match signal of the flag data in the flag register will occur; and a flag data sense circuit that senses the flag data of each of the plurality of the content addressable memory word of a second priority content addressable memory subblock before the termination of the encoding of the at least one match signal of the flag data in the flag register.

Claim 15

An encoder as claimed in claim 12, wherein the timing detection control circuit includes a number detection circuit comprising a first signal line; M current driving means for driving current into the first signal line, each of the M current driving means being connected in parallel to the first signal line; M data input lines being connected to the flag register and receiving M bits of the flag data which control the M current driving means; a second signal line; reference current driving means being connected to the second signal line; and differential current detecting means for detecting a differential current between current flowing through the first signal line and current flowing through the second signal line, wherein the number detection circuit detects a number of 0's and 1's contained in the M bits of the flag data received from the M data input lines M being an integer greater than one.

Claim 16

An encoder as claimed in claim 13, wherein each of the M current driving means comprises: a control transistor that controls an operating timing of the each of the M current driving means; and a signal voltage application transistor, a gate electrode of the signal voltage application transistor being connected one of the M data input lines.

Claim 17

An encoder as claimed in claim 14, wherein the signal voltage application transistor is connected between the control transistor and the first signal line.

Claim 18

An encoder as claimed in claim 13, wherein the differential current detection means comprises: detection start level setting means for setting a voltage difference between a detection start voltage of the first signal line and a preset voltage and between a detection start voltage of the second signal line and the preset voltage.

Claim 19

An encoder as claimed in claim 13, wherein the timing detection control circuit further includes a first inverter and a second inverter, the first and second inverters being connected between the first signal line and the differential current detection means and between the second signal line and the differential current detection means, respectively.

Claim 20

An encoder as claimed in claim 13, wherein the timing detection control circuit further includes a first transistor and a second transistor, the first and second transistors being connected between the first signal line and the differential current detection means and between the second signal line and the differential current detection means, respectively, at least one first inverter being connected between a gate electrode of the first transistor and the first signal line, and at least one second inverter being connected between a gate electrode of the second transistor and the second signal line.

Claim 21

An encoder as claimed in claim 18, wherein the timing detection control circuit further includes precharging means for precharging connections between the first and second transistors and the differential current detection means.

Claim 22

An encoder as claimed in claim 12, wherein the timing detection control circuit includes a number detection circuit comprising: a first signal line; M unit current driving means for driving current into the first signal line, each of the M unit current driving means being connected in parallel to the first signal line; a data register for holding M bits of data, each of the M bits of data controlling one of the M unit current driving means; a second signal line; N reference unit current driving means for driving current into the second signal line, each of the N reference unit current driving means being connected in parallel to the second signal line; a reference current control register that holds N bits of data, each of the N bits of data controlling one of the reference unit current driving means; reference offset current drive means connected to the second signal line; and differential current detecting means for detecting the differential current between current flowing through the first signal line and the second signal line, a reference current flowing through the second signal line and through the reference offset current drive means, wherein the number detection circuit detects a number of 0's and 1's contained in the M bits of the data held in the data register based on a number of 0's and 1's contained in the N bits of the data held in the reference current control register, M and N being integers greater than one.

Claim 23

A semiconductor integrated circuit comprising: a first signal line; M current driving means for driving current into the first signal line, each of the M current driving means being connected in parallel to the first signal line; M data input lines receiving M bits of data which control the M current driving means; a second signal line; reference current driving means being connected to the second signal line; and differential current detecting means for detecting a differential current between current flowing through the first signal line and current flowing through the second signal line, wherein the semiconductor integrated circuit detects a number of 0's and 1's contained in the M bits of the data received from the M data input lines, M being an integer greater than zero.

Claim 24

A semiconductor integrated circuit comprising: a first signal line; M current driving means for driving current into the first signal line, each of the M current driving means being connected in parallel to the first signal line; M data input lines receiving M bits of data which control the M current driving means; a second signal line; reference current driving means being connected to the second signal line; and differential current detecting means for detecting a differential current between current flowing through the first signal line and current flowing through the second signal line, wherein the semiconductor integrated circuit detects a number of 0's and 1's contained in the M bits of the data received from the M data input lines, M being an integer greater than zero.

Claim 25

A semiconductor integrated circuit as claimed in claim 21, wherein each of the M current driving means comprises: a control transistor that controls an operating timing of the each of the M current driving means; and a signal voltage application transistor, a gate electrode of the signal voltage application transistor being connected to one of the M data input lines.

Claim 26

A semiconductor integrated circuit as claimed in claim 22, wherein the signal voltage application transistor is connected between the control transistor and the first signal line.

Claim 27

A semiconductor integrated circuit as claimed in claim 21, wherein the differential current detection means comprises: detection start level setting means for setting a voltage difference between a detection start voltage of the first signal line and a preset voltage and between a detection start voltage of the second signal line and the preset voltage.

Claim 28

A semiconductor integrated circuit as claimed in claim 21, further comprising a first inverter and a second inverter, the first and second inverters being connected between the first signal line and the differential current detection means and the second signal line and between the second differential current detection means, respectively.

Claim 29

A semiconductor integrated circuit as claimed in claim 21, further comprising a first transistor and a second transistor, the first and second transistors being connected between the first signal line and the differential current detection means and between the second signal line and the differential current detection means, respectively, at least one first inverter being connected between a gate electrode of the first transistor and the first signal line, and at least one second inverter being connected between a gate electrode of the second transistor and the second signal line.

Claim 30

A semiconductor integrated circuit as claimed in claim 26, further comprising precharging means for precharging connections between the first and second transistors and the differential current detection means.

Claim 31

A semiconductor integrated circuit comprising: a first signal line; M unit current driving means for driving current into the first signal line, each of the M unit current driving means being connected in parallel to the first signal line; a data register for holding M bits of data, each of the M bits of data controlling one of the M unit current driving means; a second signal line; N reference unit current driving means for driving current into the second signal line, each of the N reference unit current driving means being connected in parallel to the second signal line; a reference current control register that holds N bits of data, each of the N bits of data controlling one of the reference unit current driving means; reference offset current drive means connected to the second signal line; and differential current detecting means for detecting the differential current between current flowing through the first signal line and the second current line, a current flowing through the second signal line and through the reference offset current drive means, wherein the semiconductor integrated circuit detects a number of 0's and 1's contained in the M bits of the data held in the data register based on a number of 0's and 1's contained in the N bits of the data held in the reference current control register, M and N being integers greater than zero.

Claim 32

A semiconductor integrated circuit comprising: a first signal line; M unit current driving means for driving current into the first signal line, each of the M unit current driving means being connected in parallel to the first signal line; a data register for holding M bits of data, each of the M bits of data controlling one of the M unit current driving means; a second signal line; N reference unit current driving means for driving current into the second signal line, each of the N reference unit current driving means being connected in parallel to the second signal line; a reference current control register that holds N bits of data, each of the N bits of data controlling one of the reference unit current driving means; reference offset current drive means connected to the second signal line; and differential current detecting means for detecting the differential current between current flowing through the first signal line and the second current line, a current flowing through the second signal line and through the reference offset current drive means, wherein the semiconductor integrated circuit detects a number of 0's and 1's contained in the M bits of the data held in the data register based on a number of 0's and 1's contained in the N bits of the data held in the reference current control register, M and N being integers greater than zero.

Claim 33

A semiconductor integrated circuit as claimed in claim 28, wherein each of the M unit current driving means comprises: a control transistor that controls an operating timing of the each of the M current driving means; and a signal voltage application transistor, a gate electrode of the signal voltage application transistor being connected to one of the M data input lines.

Claim 34

A semiconductor integrated circuit as claimed in claim 29, wherein the signal voltage application transistor is connected between the control transistor and the first signal line.

Claim 35

A semiconductor integrated circuit as claimed in claim 28, wherein the differential current detection means comprises: detection start level setting means for setting a voltage difference between a detection start voltage of the first signal line and a preset voltage and between a detection start voltage of the second signal line and the preset voltage.

Claim 36

A semiconductor integrated circuit as claimed in claim 28, further comprising a first inverter and a second inverter, the first and second inverters being connected between the first signal line and the differential current detection means and between the second signal line and the differential current detection means, respectively.

Claim 37

A semiconductor integrated circuit as claimed in claim 28, further comprising a first transistor and a second transistor, the first and second transistors being connected between the first signal line and the differential current detection means and between the second signal line and the differential current detection means, respectively, at least one first inverter being connected between a gate electrode of the first transistor and the first signal line, and at least one second inverter being connected between a gate electrode of the second transistor and the second signal line.

Claim 38

A semiconductor integrated circuit as claimed in claim 33, further comprising precharging means for precharging connections between the first and second transistors and the differential current detection means.