Associative memory

Claim 2

An associative memory for performing search and logical operations on attributive information presented as multi-digit binary associative words or sets of a plurality of binary associative indications comprising: address memory modules arranged in a matrix for storing binary data; address and digit buses of said address memory modules for recording and selecting the data stored in said address memory modules; memory elements in said address memory modules interconnected to said address and digit buses; detectors for detecting the location of data with given sets of binary associative indications, the inputs of said detectors being coupled electrically to said respective digit buses of said address memory modules; an interrogation register for storing a given set of binary associative indications which is the interrogation code, and having flip-flops with inputs and outputs, the number of said flip-flops being equal to that of binary associative indications in the interrogation code, the outputs of said flip-flops in said interrogation register being coupled electrically to said address buses of said respective address memory modules; said detectors being coincidence circuits having a numbers of inputs equal to that of said groups of said flip-flops in the interrogation register, and outputs of said detectors being electrically coupled to said inputs of said interrogation register; interrogation converters for converting the interrogation code from a binary position code into a code with a constant number of ''''1''''s, the interrogation converters being provided with inputs and outputs, said inputs of each interrogation converter being coupled electrically to said outputs of a predetermined group of said flip-flops in said interrogation register and said outputs of each interrogation converter being connected electrically to said address buses of individual ones of said address memory modules, said interrogation converters being interrogation decoders converting a binary position code into a single excited-state code.

Claim 3

A memory as claimed in claim 1, which comprises a code converter provided with inputs and outputs and intended to establish whether the number of said excited detector corresponds to the numbers of said address buses of said data storage unit; said inputs of said code converter are connected to said outputs of all said detectors; said outputs of said code are connected to said respective address buses of said data storage unit.

Claim 4

A memory as claimed in claim 1, wherein said interrogation converters are provided with long-term memory modules intended to convert the interrogation code from a binary position code into a code with a constant number of ''''1''''s, said long-term memory modules being provided with address and digit to select the codes recorded in said long-term memory modules; said address buses of each one said longterm memory module being connected to said outputs of said respective interrogation decoder, and said digit buses of each said long-term memory module being connected to said address buses of said respective address memory modules.

Claim 5

A memory as claimed in claim 1, wherein said interrogation converters are provided with long-term memory modules intended to convert the interrogation code from a binary position code into a code with a constant number of ''''1''''s; said long-term memory modules having address and digit buses to select the codes recorded in said long-term memory modules; said address buses in each said long-term memory module being connected to said outputs of said respective interrogation decoder; and said digit buses of each said long-term memory module being connected to said address buses of said respective address memory modules.

Claim 6

A memory as claimed in claim 1, wherein said interrogation converters comprise modulo 2 adders provided with inputs and outputs; each said group of said flip-flops in said interrogation register is divided into sets (consisting of subgroups; said first set comprises subgroups with a single flip-flop; said other sections comprise said subgroups with a plurality of flip-flops; said interrogation decoders and said modulo 2 adders are divided into sets; said sets consist of subgroups; said outputs of said interrogation decoder in each said subgroup are connected to said first inputs of said modulo 2 adders belonging to said subgroup; said output of each said modulo 2 adder is coupled to said second inputs of said modulo 2 adders of one of said subgroups in said next set; said outputs of said modulo 2 adders of said last set are connected to said address buses of said respective address memory modules.

Claim 7

A memory as claimed in claim 1, wherein said interrogation converters comprise modulo 2 adders having inputs and outputs; each said group of said flip-flops in said interrogation register is divided into sets consisting of subgroups; said first set comprises said subgroups with a single flip-flop; other said sections contain said subgroups with a plurality flip-flops; said interrogation decoders and said modulo 2 adders are divided into sets; said sets contain subgroups; said outputs of said interrogation decoders in each said subgroup are connected to said first inputs of said modulo 2 adders belonging to said subgroup; said output of each said modulo 2 adders is coupled to said second inputs of said modulo 2 adders in one of said subgroup of said next set; said outputs of said modulo 2 adders in said last section are connected to said address buses of respective said address memory modules.

Claim 8

A memory as claimed in claim 1, which is provided with a mask register intended to store the mask binary code wherein the positions of ''''1''''s and ''''0''''s shows the associative indications of the interrogation code irrelevant to the search operation that is being performed; said mask register comprises flip-flops equal in number to the binary associative indications in the interrogation code; said flip-flops are provided with inputs and outputs; OR circuits with inputs and outputs; said first inputs of said OR circuits are connected to said outputs of said respective flip-flops of said mask register; said second inputs of said OR circuits are connected to said outputs of said respective flip-flops in said interrogation register; said outputs of said OR circuits are connected to said inputs of said respective interrogation converters.

Claim 9

A memory as claimed in claim 1, which comprises multi-input OR circuits with inputs and outputs; and output register which is intended to receive datA derived from said respective address memory modules; said output register includes flip-flops equal in number to the binary associative indications in the interrogation code; said output register is divided into groups of said flip-flops having inputs and outputs; connected to said input of each said group of flip-flops in said output register is said output of said respective multi-input OR circuit; said inputs of said multi-input OR circuit are connected to said respective digit buses of said address memory modules; said flip-flops in said interrogation register and said flip-flops in said mask register are also divided into groups; the number of said flip-flops in said groups of said interrogation register and said mask register is equal to the number of said flip-flops in said groups of said output register.

Claim 10

A memory as claimed in claim 7, which comprises multi-input OR circuits with inputs and outputs; an output register which is intended to receive data derived from said respective address modules; said output register includes flip-flops equal in number to the indications in the interrogation code; said output register is divided into groups of said flip-flops with inputs and outputs; connected to each said group of flip-flops in said output register is said output of said respective multi-input OR circuit; said inputs of said multi-input OR circuit are connected to said respective digit buses in said address memory modules; said flip-flops in said interrogation register and said flip-flops in said mask register are also divided into groups; the number of said flip-flops of said interrogation register and of said groups mask register is equal to that of said flip-flops in said groups of said output register.

Claim 11

A memory as claimed in claim 1, which is provided with an input register intended to store a multi-digit binary code; any required logical operation can be performed on said multi-digit binary code and simultaneously on the code of any of said associative words stored in said address memory modules; said input register comprises flip-flops having inputs and outputs; the number of said flip-flops is equal to that of indications in said interrogation code; said input register is divided into groups of said flip-flops; the memory also contains coincidence circuits divided into two sets and provided with inputs and outputs; said first inputs of said coincidence circuits are connected to said outputs of said flip-flops of said respective group in said input register; and operation decoder intended to control the transfer of data to said interrogation register and said output register since respective data is transferred from said outputs of said flip-flops in said input register in the direct or reverse code depending upon the logical operation to be performed and upon the code stored in said input register; inputs and outputs of said operation decoder; said respective outputs of said operation decoder are connected to said second inputs of said coincidence circuits; said outputs of one of said sets of said coincidence circuits are connected to said inputs of said respective flip-flops in said interrogation register; said outputs of said other set of said coincidence circuits are connected to said inputs of said respective multi-input OR circuits.

Claim 12

A memory as claimed in claim 7 which comprises multi-input OR circuits; inputs and outputs of said multi-input OR circuits; an output register that serves to receive data obtained from respective address memory modules; flip-flops of said output register, equal in number to the indications in the interrogation code; groups of said flip-flops of said output register; inputs and outputs of said groups connected to said input of each said group of flip-flops in said output register is said output of said respective multi-input OR circuit; said inputs of said multi-input OR circuit are connected to said respective digit buses of said address memory modules; groups of said flip-flops in saId interrogation register and groups of said flip-flops in said mask register; the number of said flip-flops in said groups of said interrogation register and said mask register is equal to that of said flip-flops in said groups of said output register; an input register intended to store a multi-digit binary code; said multi-digit binary code and, at the same time the code of any other said associative word stored in said address memory modules can be subjected to any required logical operation; flip-flops of said input register; inputs and outputs of said flip-flops; the number of said flip-flops is equal to that of indications in said interrogation code; said groups of said flip-flops in the input register; coincidence circuits; two sets of said coincidence circuits; inputs and outputs of said coincidence circuits; said first inputs of said coincidence circuits are connected to said outputs of said flip-flops in said respective group of said input register; said memory additionally comprises an operation decoder provided with inputs and outputs and intended to control the transfer of data to said interrogation register and said output register since respective data is transferred from said outputs of said flip-flops in said inputs register in the direct or reverse code depending upon the logical operation to be performed and upon the code stored in said input register; said respective outputs of said operation decoder are connected to, said second inputs of said coincidence circuits; said outputs of one of said sections of said coincidence circuits are connected to said inputs of said respective flip-flops in said interrogation register; said outputs of said other section of said coincidence circuits are connected to said inputs of said respective multi-input OR circuits.

Claim 13

A memory as claimed in claim 1, wherein said group of flip-flops in said input and output registers are combined to form shift registers while said groups of flip-flops in said mask register are combined to form ring shift registers.

Claim 14

A memory as claimed in claim 7, wherein said respective groups of flip-flops in said input and output registers are combined to form shift registers, while said groups of flip-flops in said mask register are combined to form ring shift registers.

Claim 15

A memory as claimed in claim 8, which is provided with an input register intended to store a multi-digit binary code; said multi-digit binary code and, at the same time, any of said associative words stored in said address memory modules can be subjected to any required logical operation; said input register comprises flip-flops having inputs and outputs; the number of said flip-flops is equal to that of indications in said interrogation code; said input register is divided into groups of said flip-flops; the memory also contains coincidence circuits divided into two sets and provided with inputs and outputs; said first inputs of said coincidence circuits are connected to said outputs of said flip-flops of said respective group in said input register; in addition the memory comprises an operation decoder provided with inputs and outputs and intended to control the transfer of data to said interrogation register and said output register since respective data is transferred from said outputs of said flip-flops in said input register in the direct or reverse code depending upon the logical operation to be performed and upon the code stored in said input register; said respective outputs of said operation decoder are connected to said second inputs of said coincidence circuits; said outputs of said one set of said coincidence circuits are connected to said inputs of said respective flip-flops in said interrogation register, said outputs of said second set of said coincidence circuits are connected to said inputs of respective said multi-input OR circuits; said groups of flip-flops in said input and output registers are combined to form shift registers; said groups of flip-flops in said mask register are combined to forM ring shift registers.

Claim 16

A memory as claimed in claim 1, which comprises additional decoders having inputs and outputs; each of said additional decoders performs the function of a number of detectors; the memory also comprises a priority circuit having inputs and outputs which is intended to select the detectors in the required sequence, the detectors corresponding to said required set of binary associative indications in the course of a multidigit access procedure, i.e., when several said associative words are being selected simultaneously; said inputs of said priority circuit are connected to said first outputs of all said additional decoders; in addition the memory contains also ''''0'''' signal and ''''1'''' signal coincidence circuits having inputs and outputs; said address memory modules are combined to form sets of m address memory modules used to store m-digit binary associative indications, which allows a set of ''''m'''' address memory modules to record up to 2m - 1 different associative indications on ''''m'''' digit buses, and, hence, up to 2m - 1 different said associative words; similar said digit buses of said address memory modules of each set are connected to said inputs of said ''''0'''' signal and ''''1'''' signal coincidence circuits which correspond to a given set; said outputs of said coincidence circuits in each set are connected to said inputs of said respective additional decoders.

Claim 17

A memory as claimed in claim 1, which is provided with a data storage unit intended to store data every word of which corresponds to a given set of said binary associative indications stored in said address memory modules that form the storage unit to store data indications; said data storage unit contains memory elements; said memory elements are interconnected through address buses, write digit buses and read digit buses and combined to form K-digit cells; in addition, the memory comprises a data register containing flip-flops with inputs and outputs; the number of said flip-flops is equal to that of digits in a cell of said data storage unit; said read digit buses of said data storage unit are connected to said inputs of respective said flip-flops in said data register, said write digit buses of said data storage unit are connected to said outputs of said respective flip-flops in said data register; said address buses of said data storage unit are coupled electrically to said outputs of said respective detectors; each said cell of said data storage unit is provided with additional memory elements used to record the code of a given associative word that is positioned in accordance with a given said cell in said data storage unit; said data register is provided with additional flip-flops intended to store the code arriving from said interrogation register to be recorded in said data storage unit; said additional flip-flops in said data register also serve to receive codes from said data storage unit, the number of said additional memory elements in each said cell of said data storage unit and the number of said additional flip-flops in said data register are equal to that of said flip-flops in said interrogation register; said second inputs of said additional flip-flops in said data register are connected to said outputs of similar flip-flops in said interrogation register; said inputs of said flip-flops in said interrogation register are connected to said outputs of said similar additional flip-flops in said data register.

Claim 18

A memory as claimed in claim 1, which comprises a digit-by-digit comparison circuit having inputs and outputs; said first inputs of said digit-by-digit comparison circuits are connected to said outputs of said respective flip-flops in said interrogation register; said second inputs of said digit-by-digit comparison circuit are connected to said outputs of said respective additional flip-flops in said data register.

Claim 19

A memory as claimed In claim 16, which comprises a digit-by-digit comparison circuit having inputs and outputs; said first inputs of said digit-by-digit comparisonx circuit are connected to said outputs of said respective flip-flops in said interrogation register; said second inputs of said digit-by-digit comparison circuit are connected to said outputs of said respective additional flip-flops in said data register.

Claim 20

A memory as claimed in claim 6, which comprises a digit-by-digit comparison circuit having inputs and outputs; said first inputs of said digit-by-digit comparison circuit are connected to said outputs of said respective flip-flops in said interrogation register; said second inputs of said digit-by-digit comparison circuit are connected to said outputs of said respective additional flip-flops in said data register; in addition, the memory comprises a code converter provided with inputs and outputs and intended to establish whether the number of excited said detector corresponds to the numbers of said address buses of said data storage unit; said inputs of said code converter are connected to said outputs of all said detectors; said outputs of said code converter are connected to said respective address buses of said data storage unit.