US4890260A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Content addressable memory array with maskable and resettable bits
Assignee: GlobalFoundries Inc
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Filing: 1988-05-11
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Granted: 1989-12-26
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Expires: 2008-05-11
Abstract
Abstract A content addressable memory array (11) includes an array of cells containing bits configured in N bits for each word, a first one of the bits in each of the words being a skip bit, the array (11) being searched on the basis of the contents of the words to locate selected words, a second one of the bits in each word being identified as an empty bit, means for examining the words to detect the presence therein of skip bits, means for examining the words to detect the presence therein of empty bits, and means responsive to detection of one of the skip bits in one of the words for eliminating the word containing the detected skip bit from said search.
Inventors
- 👤 Patrick T. Chuang
- 👤 Robert L. Yau
- 👤 Hiroshi Yoshida
- 👤 Moon-Yee Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:24
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04; G06; G06F; G06F16/00; G06F16/90; G06F16/903; G06F16/90335; G06F16/90339
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
165 words
A content addressable memory array comprising an array of M words, each word containing bits configured in N bits for each word, a first one of said bits in each of said words being a settable skip bit; means for searching said array on the basis of the contents of said words to locate selected words; a second one of said bits in each of said words being a settable empty bit; means for setting selected ones of said skip bits to a skip condition; means for examining each of said words to detect the presence therein of a set skip bit therein; means for setting selected ones of said empty bits to an empty condition; means for examining said each of said words to detect the presence therein of a set empty bit therein; and means responsive to detection of one of said skip bits in any of said words for eliminating any of said words containing said detected skip bit from said search.
Claim 2
Dependent Claim
165 words
A content addressable memory array comprising an array of M words, each word containing bits configured in N bits for each word, a first one of said bits in each of said words being a settable skip bit; means for searching said array on the basis of the contents of said words to locate selected words; a second one of said bits in each of said words being a settable empty bit; means for setting selected ones of said skip bits to a skip condition; means for examining each of said words to detect the presence therein of a set skip bit therein; means for setting selected ones of said empty bits to an empty condition; means for examining said each of said words to detect the presence therein of a set empty bit therein; and means responsive to detection of one of said skip bits in any of said words for eliminating any of said words containing said detected skip bit from said search.
Claim 3
Dependent Claim
49 words
A memory array in accordance with claim 1 including means for setting said skip bit in selected ones of said words at a predetermined first value to cause said skip bit examining means to skip searching those word locations having said skip bit set at said predetermined first value.
Claim 4
Dependent Claim
49 words
A memory array in accordance with claim 1 including means for setting said empty bit in selected ones of said words at a predetermined first value to cause said empty bit examining means to skip searching those word locations having said empty bit set at said predetermined first value.
Claim 5
Dependent Claim
45 words
A memory array in accordance with claim 1 including means for setting all of said empty bits in each of said words to a first predetermined value to empty all of said words in said memory array to reset said array to an empty condition.
Claim 6
Dependent Claim
52 words
A memory array in accordance with claim 1 including means for setting said empty bit in selected ones of said word to a first predetermined value to cause said empty bit examining means to empty said bits in those of said words in which said empty bit has said first predetermined value.
References Cited (Backward Citations)
US4670858A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-25 | 1993-06-26 | 1993-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-25 | 1997-06-26 | 1997-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-25 | 2001-06-26 | 2001-12-26 | $7700.00 | Window Closed / Lapsed |