US5036486A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Associative memory device
Assignee: Hitachi Ltd
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Filing: 1990-07-09
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Granted: 1991-07-30
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Expires: 2010-07-09
Abstract
Abstract In associative memory device, a search key is stored in the first storage element and a storage key is stored in the second storage elements, respectively via a first data bus. The search key is supplied to the comparator via a second data bus, and the storage key stored in the second storage element is supplied to the comparator. The comparator compares the search key with the storage key. When the storage key is consistent with the search key, the comparator delivers as the associative operation results a comparison consistency output signal to a priority encoder circuit which outputs code information having a limited bit length. This code information is transferred to CPU via a selector circuit. If the comparator delivers a comparison inconsistency output signal, this signal is directly passed to CPU via the priority encoder circuit, so that the contents of the first storage element is rewritten. The first and second storage elements are designated by an address signal and data is read or written via the first data bus, so that they are used as a usual memory device.
Inventors
- 👤 Kouki Noguchi
- 👤 Mitsuru Akizawa
- 👤 Kanji Kato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 05:33
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04; G06; G06F; G06F16/00; G06F16/90; G06F16/903; G06F16/90335; G06F16/90339
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
274 words
An associative memory device comprising: a first storage element for storing data of a predetermined bit length; a plurality of second storage elements for storing data of said predetermined bit length; a first data bus connecting to said first storage element and said plurality of second storage elements so as to read and write said data of said predetermined bit length; a second data bus transferring said data of said predetermined bit length stored in said first storage element; a plurality of comparators coupled to said second storage elements and said second data bus for comparing said data of said predetermined bit length stored in said first storage element with said data of said predetermined bit length stored in said plurality of second storage elements; an output section connected to said plurality of comparators to receive the comparison results outputted from said plurality of comparators; and a selector section having a first terminal, second terminal and third terminal, said first terminal being connected to said first data bus, said second terminal being connected to an output line of said output section, and said third terminal being connected to a data signal line for inputting and outputting signals of the device, said selector section responsive to a predetermined state of a control signal for allowing a signal transmission between said first terminal and third terminal and inhibiting a signal transmission between said second terminal and third terminal, and responsive to a state of said control signal different from said predetermined state for inhibiting a signal transmission between said first terminal and third terminal and allowing a signal transmission between said second terminal and third terminal.
Claim 2
Dependent Claim
274 words
An associative memory device comprising: a first storage element for storing data of a predetermined bit length; a plurality of second storage elements for storing data of said predetermined bit length; a first data bus connecting to said first storage element and said plurality of second storage elements so as to read and write said data of said predetermined bit length; a second data bus transferring said data of said predetermined bit length stored in said first storage element; a plurality of comparators coupled to said second storage elements and said second data bus for comparing said data of said predetermined bit length stored in said first storage element with said data of said predetermined bit length stored in said plurality of second storage elements; an output section connected to said plurality of comparators to receive the comparison results outputted from said plurality of comparators; and a selector section having a first terminal, second terminal and third terminal, said first terminal being connected to said first data bus, said second terminal being connected to an output line of said output section, and said third terminal being connected to a data signal line for inputting and outputting signals of the device, said selector section responsive to a predetermined state of a control signal for allowing a signal transmission between said first terminal and third terminal and inhibiting a signal transmission between said second terminal and third terminal, and responsive to a state of said control signal different from said predetermined state for inhibiting a signal transmission between said first terminal and third terminal and allowing a signal transmission between said second terminal and third terminal.
Claim 3
Dependent Claim
47 words
An associative memory device according to claim 1, wherein said data of said predetermined bit length is stored in said first storage element and said plurality of second storage elements via said third terminal and first terminal of said selector section and via said first data bus.
Claim 4
Dependent Claim
44 words
An associative memory device according to claim 2, wherein said data of said predetermined bit length stored in said first storage element is a search key, and said data of said predetermined bit length stored in said second storage elements is a storage key.
Claim 5
Dependent Claim
99 words
An associative memory device according to claim 3, including an address decoder for selecting at least one of said first storage element and said plurality of second storage elements in response to an address signal used for storing said search key and storage key in said first storage element and said plurality of second storage elements prior to an associative operation, and for supplying a control signal to said selector section so that code information in accordance with set associative operation results from said output section is transmitted from said second terminal to third terminal of said selector section.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-29 | 1995-01-28 | 1995-07-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-29 | 1999-01-28 | 1999-07-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-29 | 2003-01-28 | 2003-07-30 | $7700.00 | Window Closed / Lapsed |